Abstract: A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.

Abstract: A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where the memory device is disabled in response to receiving wrong passcodes repeatedly for a maximum number of tries.

Abstract: A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.

Abstract: A memory device implements a memory read training method using a dedicated read command to retrieve training data from a register for performing memory read training while the memory device remains operating in the normal operation mode. Subsequent to the memory read training, the memory device may then receive the normal read command to read data from the memory cell array or the normal write command to write data to the memory cell array. In this manner, memory read training is performed simply by issuing read commands and carrying out read operations without requiring the memory device to enter and exit special memory read training mode for performing calibration.

Abstract: Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.

Abstract: A clock timing adjust circuit is incorporated in a clocked integrated circuit to detect an input clock frequency and to adjust the timing latency of an internal control signal for accessing a memory element in the clocked integrated circuit. The clock timing adjust circuit introduces an adjustable timing latency to an internal control signal derived from the command signal. The clock timing adjust circuit operates to adjust the timing latency of the control signal to cause clock based operations to either be advanced or delayed by one or more clock cycles in response to the clock frequency detection. In one embodiment, the clock timing adjust circuit includes a clock frequency detect circuit and a latency adjust circuit. The clock timing adjust circuit can operate at both high and low clock frequencies to ensure that undesired data collision events are obviated without introducing unnecessary delays.

Abstract: An LED controller for a multiple LED channel system using PWM method for LED dimming function incorporates a digital dimming control circuit to generate the PWM signals for driving the LED channels to spread out or cancel out the power supply transients generated by the LED transient current during PWM modulation for dimming operation. The digital dimming control circuit implements a power supply transient reduction method whereby the active period of the PWM signals for some of the LED channels are shifted within the switching cycle to align at least some of the rising signal edges with some of the falling signal edges so as to cancel out the voltage transients on the LED power rails generated at the signal transitions. Furthermore, the rising and falling signal edges that are not lined up are spread out through the PWM switching cycle so that the power supply transients are spread out.

Abstract: A memory device incorporates a serial data bus coupled to a serial bus control circuit to provide access to error correction event notification information and error correction function configuration information. In some embodiments, the serial bus control circuit is in communication with a set of registers storing error correction event information and error correction function configuration information. The serial data bus enables access to the error correction control functions and to the error correction event notification information without interfering with and independent of the normal memory operation of the memory device.

Abstract: A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring modifications to the memory controller used to control and communicate with the memory device.

Abstract: Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.

Abstract: An LED controller for a multiple LED channel system using PWM method for LED dimming function incorporates a digital dimming control circuit to generate the PWM signals for driving the LED channels to spread out or cancel out the power supply transients generated by the LED transient current during PWM modulation for dimming operation. The digital dimming control circuit implements an audible noise reduction method whereby the active period of the PWM signals for some of the LED channels are shifted within the switching cycle to align at least some of the rising signal edges with some of the falling signal edges so as to cancel out the voltage transients on the LED power rails generated at the signal transitions. Furthermore, the rising and falling signal edges that are not lined up are spread out through the PWM switching cycle so that the power supply transients are spread out.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

Abstract: A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Abstract: A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with reduced sense margins are refreshed.

Abstract: A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device.

Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.