Abstract: A commutator circuit has a plurality of stages connected in series, each stage having a plurality of data inputs and a like plurality of data outputs with the data outputs of each stage being connected in one-to-one correspondence to the data inputs of the next stage. Each stage includes a plurality of data transposition circuits each connected between a respective pair of the data inputs and a respective pair of the data outputs for that stage. Each data transposition circuit includes two 2-to-1 selector switches each having two inputs connected to respective ones of the pair of data inputs and a single output connected to a respective one of the pair of data outputs, a first delay element connected between one of the data inputs and the two selector switches, and a second delay element connected to the output of one of the selector switches.