Abstract: Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuation on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block.

Abstract: A multichip integrated circuit package comprises a substrate having a flat upper surface to which is affixed one or more integrated circuit chips having interconnection pads. A polymer encapsulant completely surrounds the integrated circuit chips. The encapsulant is provided with a plurality of via openings therein to accommodate a layer of interconnection metallization. The metallization serves to connect various chips and chip pads with the interconnection pads disposed on the chips. In specific embodiments, the module is constructed to be repairable, have high I/O capability with optimal heat removal, have optimized speed, be capable of incorporating an assortment of components of various thicknesses and function, and be hermetically sealed with a high I/O count. Specific processing methods for each of the various module features are described herein, along with additional structural enhancements.