Abstract: A programmable timer is disclosed for use in conjunction with a microcontroller circuit. The timer is used as part of a time slice arbiter in a real time operating system, which arbiter manages device routines by allocating them to distinct code time slices executable by such microcontroller. The set up of time slices, including their number, sequence, duration, etc., can be configured and optimized to achieve a desired system performance level based on characteristics of an associated system bus, devices on the bus, etc. The timer operates as a hardware controller to direct the interrupt handler to various entry points in the corresponding routines associated with interrupt based devices on a system bus.

Abstract: A self-adjusting apparatus including a clock generator built within an IC generates an adjusted internal oscillating clock signal by referring to an external target signal while the IC is running in a normal mode, and a method for adjusting the internal oscillating clock signal of an IC by using the apparatus. While an IC is operating in a normal mode, which is a more power-consuming mode, the apparatus adjusts the internal oscillating clock signal of the IC by referring to the frequency of an external clock signal generated by an external clock generator. When the IC is forced to run in a power-down mode, which consumes less power, the self-adjusting apparatus is still able to provide a precise internal oscillating clock signal required for operating the electronic circuit without the presence of an external clock signal.

Abstract: A high-speed rail-to-rail comparator is described. The comparator has two PMOS transistors, two NMOS transistors, a current source and two voltage-dropped components. A first PMOS transistor has a source terminal coupled to a first voltage source and a gate terminal and a drain terminal coupled to each other. A second PMOS transistor has a source terminal coupled to the first voltage source, and a gate terminal of the second PMOS transistor coupled to the gate terminal of the first PMOS transistor. A first NMOS transistor has a drain terminal coupled to the drain terminal of the first PMOS transistor and a gate terminal coupled to a reference signal. A second NMOS transistor has a drain terminal of the first NMOS transistor coupled to the drain terminal of the second PMOS transistor and coupled to an output terminal. A gate terminal of the second NMOS transistor is coupled to an input terminal and a source terminal of the second NMOS transistor is coupled to a source terminal of the first NMOS transistor.

Abstract: A circuit and method are provided for initializing configuration registers in a bus bridge controller so that peripheral devices can acquire functionality prior to initialization by a normal system Basic Input/Output System (BIOS) routine. The initialization information is stored in a supplemental configuration Electronically Erasable Programmable Read Only Memory (EEPROM), separate from a conventional system BIOS ROM. In addition, the register configuration information is stored in a flexible format so that only certain devices are pre-configured, or that certain devices are initialized before others. The invention has particular usefulness in personal computing systems which include a Peripheral Component Interconnect (PCI) bus, an ISA bus, and a system management bus (SMB) for providing access to the EEPROM.

Abstract: Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory.