Abstract: An image processing device comprising a synchronization unit (25) for generating a luminance (Y?) from the sum of pixel signals R, Gr, Gb, B, for subtracting the R pixel signal and the B pixel signal from the sum of the Gr pixel signal and Gb pixel signal so as to generate a first color difference (C1), and for calculating a difference between the R pixel signal and the B pixel signal to generate a second color difference (C2), a pseudo-color suppression unit (31) for performing pseudo-color suppression of the first color difference (C1) and/or the second color difference (C2), a color space conversion unit (37) for converting the luminance Y?, the first color difference (C1), the second color difference (C2), into a predetermined color space to generate YUV color information.

Abstract: A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

Abstract: Method for parallel approximation of distance maps on a discrete representation of a manifold, the method comprising: for at least one Euclidean grid applied on the discrete representation of a manifold, iterating over rows of the Euclidean grid in a first direction, and for each row currently visited during the iterating in the first direction, calculating a distance value for each single cell of the currently visited row in parallel, wherein the calculating is carried out according to a predefined approximation rule, using a distance value calculated for each one of respective cells of a row visited immediately before the currently visited row, wherein the cells of the row visited before the currently visited row are adjacent to the single cell in the Euclidean grid.

Abstract: A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.