Abstract: Some forms relate to a method of making a stretchable computing system. The method includes attaching a first set of conductive traces to a stretchable member; attaching a first electronic component to the first set of conductive traces; adding a first set of flexible conductors to the stretchable member such that the first set of flexible conductors is electrically connected to the first set of conductive traces; adding stretchable material to the stretchable member such that the first set of conductive traces is surrounded by the stretchable member; forming an opening in the stretchable member that exposes the first set of conductive traces; and attaching a second set of conductive traces to the stretchable member such that the second set of conductive traces fills the opening to form a via in the stretchable member that electrically connects the first set of conductive traces with the second set of conductive traces.

Abstract: A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

Abstract: A method and apparatus are provided that determine the suitability of an image for use by an object tracking system. According to one embodiment of the present invention an image is preprocessed to separate one or more objects to be tracked from the rest of the image and compute statistics for the one or more objects to be tracked and the rest of the image. A quality measure is generated based on the statistics for the one or more objects to be tracked and the rest of the image that indicates the suitability of the image for use by an object tracking system.

Abstract: A system assembly for the retention of heatsinks, in particular, high-mass heatsinks, is disclosed. The system assembly includes a backplate with standoffs extending transverse to a system board, for securing a heatsink to the system board. The standoffs effectively distribute the mass of the heatsink away from the system board, the processor, and socket, minimizing damage to these components. A TIM spring disposed within the backplate provides upward pressure to the system assembly to uniformly spread a thermal interface material between the processor and the heatsink, thereby facilitating effective heat transfer.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: An apparatus for retaining a processor card of a processor card assembly in a connected position including a first and a second retention arm having a first and a second window respectively for accepting a first and a second latch of the processor card assembly for latching the processor card assembly to the apparatus. Each retention arm further includes a first and a second support and fastening feature disposed at opposite sides of a bottom end of the retention arm. Each support and fastening feature includes at least one capturing arm for capturing in place a threaded bushing for accepting a threaded fastener for fastening the apparatus to the motherboard.

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. According to one embodiment, the voltage transients are due to electrostatic discharge (ESD). The arrangement comprises a latch for coupling to an input pad of the integrated circuit. The latch asserts a first signal in response to sensing the occurrence of the voltage transient at the input pad. A transient protection circuit is coupled to the input pad for coupling the input pad to ground in response to the latch asserting the first signal such that current associated with the voltage transient is shunted to ground. A circuit is coupled to the latch for preventing the latch from asserting the first signal in response to the occurrence of the voltage transient if a predetermined condition exists.

Abstract: Apparatus and a method for testing each write to memory to determine whether it is addressed to an address identical to that of another write to memory waiting to be processed and merging the valid data in any subsequent writes to the same address until a memory write occurs.

Abstract: A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress.