Patents Assigned to Intel Corporatioin
  • Circuits and methods for selectively latching the output of an adder
    Patent number: 6731138
    Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: May 4, 2004
    Assignee: Intel Corporatioin
    Inventors: Meiram Heller, Eitan Emanuel Rosen