Abstract: Data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret. A container manager, executable by the processor, creates a secured container including report generation logic that determines measurements of the secured container, generates a report according to a defined report format, and sends a quote request including the report. The defined report format includes a field to include the measurements and a field to include the data integrity code, and the report format is compatible for consumption by any one of a plurality of different quote creator types.
Type:
Grant
Filed:
July 1, 2022
Date of Patent:
November 7, 2023
Assignee:
Intel Corporation, Inc.
Inventors:
Vincent R. Scarlata, Carlos V. Rozas, Baiju Patel, Barry E. Huntley, Ravi L. Sahita, Hormuzd M. Khosravi
Abstract: A mechanism is described for facilitating power extension service at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes calculating potential power saving by one or more of a plurality of power-saving techniques supported by a computing device. The calculating includes identifying the one or more of the plurality of power-saving techniques that are available for selection and an expected amount of power to be saved with the one or more of the plurality of power saving techniques. The method may further include generating a list identifying the one or more of the plurality of power-saving techniques and relevant information resulting from the calculation, and displaying the list.
Abstract: A system and method of creating affinity groups of portable communication device users, and distributing targeted content to said users is disclosed. The user affinity groups may be formed by comparing user profiles with each other or with a predefined affinity group profile definition.
Type:
Application
Filed:
November 18, 2013
Publication date:
March 27, 2014
Applicant:
Intel Corporation, Inc.
Inventors:
Daniel Simon, Mark Ford Westling, Phillip Wherry
Abstract: A mechanism is described for chimney-based cooling of computer components. A method of embodiments of the invention includes determining heat-emitting components of a computing device. The method further includes coupling a chimney to one or more of the heat-emitting components such that chimney effect of the chimney is used to guide air associated with a component in and out of the chimney.
Type:
Application
Filed:
December 22, 2010
Publication date:
March 29, 2012
Applicant:
Intel Corporation, Inc.
Inventors:
Anandaroop Bhattacharya, Mark MacDonald, Sanjay Vijayaraghavan
Abstract: The present methods, compositions and systems are concerned with biomolecule 130 detection, identification and/or quantification by rolling circle amplification (RCA) and Raman detection. In particular embodiments of the invention, the RCA is exponential RCA or linear RCA. In some embodiments of the invention, the Raman detection is SERS or SERRS. The circular DNA template 150, 210, 310 to be amplified may comprise one or more polythymidine 320 residues, resulting in amplification products 170, 230, 250, 330, 410 containing multiple polyadenylate 340, 420 residues. The polyadenylates 340, 420 may be directly detected by Raman detection. Alternatively, one or more Raman labels may be incorporated into the amplification products 170, 230, 250, 330, 410 to facilitate Raman detection.
Abstract: A portable, low power base station is configured to convey wireless traffic between a mobile station and a conventional wireless network via the Internet. The base station is configured to connect to the Internet at a user-selected location and establishes a small area of wireless coverage within a greater macrocell network. The user sets the operating parameters of the base station.
Abstract: An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories.
Type:
Grant
Filed:
December 9, 1996
Date of Patent:
September 15, 1998
Assignee:
Intel Corporation, Inc.
Inventors:
Gene F. Young, Roy M. Stevens, Larry C. James
Abstract: A three-dimensional floating gate memory cell including an integral select gate transistor is disclosed. Source and drain are formed in a silicon substrate wherein the drain is formed under a slot which has been etched into the body of the substrate. In this way, the channel defined between the source and drain has both horizontal and vertical regions. The cell also includes a floating gate, which is completely surrounded with insulation, and a control gate which is insulated above and extends over the floating gate. The control gate is also insulated above and extends over the vertical portion of the channel within the slot. This allows the second gate member to regulate the current flowing in the vertical portion of the channel; that is, the second gate member and the vertical channel section form an integral select device.