Abstract: A compiler may identify tensor operations in a deep learning model. For each tensor operation, the compiler may generate schedules arranged in a hierarchical structure. The compiler may select one or more schedules from the lowest level of the hierarchical structure by inputting the schedules at the lowest level and optionally other data into a trained model. The trained model may output a selection of one or more schedules. After selecting schedules for the tensor operations, the compiler may generate a graph including edges representing connections between the schedules. Each edge connects a schedule for a producing tensor operation to a schedule for a consuming tensor operation. The compiler may determine a weight for each edge and select a path based on the weights of the edges. The schedules along the path constitute a combined schedule to be used to transform loops of the deep learning model.

Abstract: Disclosed herein are examples of integrated circuit (IC) structures with engineered substrates that may mitigate problems that may be encountered when epitaxially growing III-N semiconductor materials, such as gallium nitride. Examples of engineered substrates for epitaxial growth of III-N semiconductor materials and III-N transistors include a thicker silicon substrate, a lattice-matched substrate, and a trap-rich silicon-on-insulator (SOI) substrate. In one example, an IC structure includes a lattice-matched and/or SOI substrate including a polycrystalline semiconductor material, an oxide layer over the polycrystalline semiconductor material, and a monocrystalline semiconductor material over the oxide layer. The IC structure may include a III-N semiconductor material over the monocrystalline silicon layer.

Abstract: Technologies for thermal management of the base die in high-bandwidth memory (HBM) die stacks are disclosed. In an illustrative embodiment, the interface logic region of the base die is a hot spot, as all of the high-speed signals into and out of the HBM die stack pass through the interface logic region. The memory dies stacked above the base die may not extend all the way across the HBM die stack, leaving space above the interface logic region of the base die. A stack of one or more heat transfer layers can be deposited on the base die above the interface logic region, removing heat and conducting it up to the top of the HBM die stack, where a heat sink or integrated heat spreader may be. The stack of one or more heat transfer layers may be any suitable material, such as silicon, dielectric packaging mold, etc.

Abstract: Accordingly, substrates for multi-die IC packages, and related assemblies, devices and methods, are disclosed herein. For example, in some embodiments, a substrate may include a dielectric material having a first surface and an opposing second surface, wherein the first surface includes a protruding portion; a conductive contact on the protruding portion of the first surface of the dielectric material; and a conductive pathway through the dielectric material and coupled to the conductive pathway. In some embodiments, the protruding portion of the first surface of the dielectric material has a thickness between 3 microns and 10 microns.

Abstract: Technologies for base die placement in high-bandwidth memory (HBM) systems are disclosed. In an illustrative embodiment, the base die or interface die for an HBM die stack may be positioned in the middle of the HBM die stack. Positioning the interface die in the middle can balance timings between various memory dies in the HBM die stack better than positioning the interface die at the bottom. The balanced timing can improve performance, allowing for higher bandwidth and/or more HBM memory dies in the stack. Through-silicon vias extend from the interface die, through one or more memory dies, and to microbumps at the bottom of the HBM die stack. In some embodiments, the interface die may be positioned closer to or at the top of the HBM die stack, closer to the heat sink. Such a placement may facilitate heat removal from the interface die.

Abstract: Disclosed herein are examples of integrated circuit (IC) structures fabricated using semiconductor/dielectric interface engineering techniques for III-N transistors. Semiconductor/dielectric interface engineering techniques for III-N transistors may include, for example, a thermal treatment, a chemical treatment, a plasma treatment, and/or introduction of an interlayer (e.g., between the III-N semiconductor material and the gate insulator material and/or between the polarization material and an insulator material). The resulting semiconductor/dielectric interface may in turn result in higher performance and/or higher gate dielectric reliability.

Abstract: A machine-readable medium having program code stored thereon which, when executed by one or more processors, causes the operations of: isolating a static resource associated with a graphics processor, the static resource to be utilized by a plurality of virtualized instances of the graphics processor; configuring, by a virtual machine monitor (VMM) or other trusted supervisory software, a shared memory partition corresponding to a physical function; uploading the static resource to the shared memory partition and configuring the shared memory partition as read-only with respect to the virtualized instances; mapping the shared region to each of a plurality of guest virtual machines (VMs); and wherein each guest VM is to locate and directly access the shared memory partition.

Abstract: This disclosure describes systems, methods, and devices for receiving network assisted multi-user multiple input multiple output (MU-MIMO) signaling. A user equipment (UE) device may decode a MU-MIMO set-up field in a radio resource control (RRC) message sent from a Next Generation NodeB device; determine, based on at least two bits in the MU-MIMO set-up field, that a MU-MIMO transmission is enabled; and determine, based on that least two bits, a modulation scheme for co-scheduled UE devices.

Abstract: Logic may determine, based on a PRS configuration, a frequency range of a PRS, wherein the PRS configuration defines resource blocks of frequency layers of the PRS. Logic may determine a number of frequency hops between frequency layers associated with the frequency range of the PRS during repetitions of one measurement gap based on a per UE measurement gap configuration or up to two measurement gaps based on a per frequency range (FR) measurement gap configuration, to perform measurements of the PRS within at least one measurement delay. Logic may perform the number of frequency hops and measurements of the PRS during each of the repetitions of the one measurement gap or the up to two measurement gaps. And logic may cause transmission of at least one positioning measurement report via the interface.

Abstract: Systems and methods are provided for context-aware, real-time speaker prioritization and enhancement. A speech encoder is provided that enables real-time prioritization of the speaker who is contextually most important rather than merely the loudest. The system uses a single-pass architecture and integrates comprehensive semantic analysis with acoustic speaker identification so that speaker focus is directed based on contextual importance rather than acoustic prominence. Comprehensive semantic analyses can include content-relevance assessment, vocabulary domain detection, identification of speaker roles, evaluation of dialogue context, and tracking of conversational continuity. The system simultaneously generates a transcript of the prioritized speech. A self-calibration loop monitors enhanced audio and transcript quality indicators and automatically adjusts fusion weights and enhancement parameters over time, enabling robust performance across changing acoustic conditions and conversation styles.

Abstract: Disclosed herein is a fabrication method that allows forming backside source and/or drain (S/D) contacts that are self-aligned to corresponding S/D regions of a transistor, and related integrated circuit (IC) structures and devices. In one aspect, a resulting IC structure may include a transistor and a nanoribbon comprising a semiconductor material. A channel portion of the transistor includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side. A first conductive contact is at the front side of the channel portion and is in conductive contact with a first S/D region of the transistor. A second conductive contact is at the back side of the channel portion and is in conductive contact with a second S/D region of the transistor. Furthermore, the second conductive contact is self-aligned to the second S/D region of the transistor.

Abstract: AI-based workload scheduling across an iGPU and dGPU. For example, one embodiment of an apparatus comprises: graphics processing circuitry of an in-vehicle infotainment (IVI) system, the graphics processing circuitry including an integrated graphics processor (iGPU) and a discrete graphics processor (dGPU); a processor to execute program code from a memory to implement a graphics task scheduler, the graphics task scheduler to operate in accordance with a trained machine-learning (ML) model to: determine features associated with a next artificial intelligence (AI) or 3D graphics task to be executed by the graphics processing circuitry; determine metrics associated with a current state, the metrics to include: current power consumption conditions, current thermal conditions, and current resource utilization conditions; and select either the iGPU or the dGPU to execute the next AI or 3D graphics task based on at least one of: the features and the metrics associated with the current state.

Abstract: Techniques are provided herein to form an integrated circuit having different semiconductor devices with different backside epitaxial regions to improve the ohmic contact between the backside epitaxial regions and backside contact structures. FETs (field effect transistors) each includes semiconductor material extending in a first direction between source and drain regions. Different epitaxial grown material may be formed on the underside of the n-channel source or drain regions compared to the p-channel source or drain regions. Epitaxial growth on the underside of a p-channel source or drain region can include silicon germanium (SiGe) doped with both boron (B) and gallium (Ga) with a higher concentration of germanium (Ge) compared to the p-channel source or drain region. Additional epitaxial growth on the underside of a n-channel source or drain region can include silicon (Si) doped with a higher electrically active % of phosphorous (P) compared to the n-channel source or drain region.

Abstract: Disclosed herein are integrated circuit (IC) structures with nanoribbon transistors and C-clamp source and/or drain (S/D) contacts, and related methods and devices. In one aspect, an example IC structure may include a transistor having a channel portion in a nanoribbon, and a conductive contact to a region of the transistor, where the region is one of a source region or a drain region of the transistor and where, in a cross-sectional side view of the IC structure, the conductive contact has a C-shape.

Abstract: Disclosed herein are integrated circuit (IC) structures with convex interfaces at source/drain (S/D) contacts, and related methods and devices. In one aspect, an example IC structure includes a nanoribbon transistor including a S/D region and further includes a contact structure connected with the S/D region, where, in a cross-sectional side view of the IC structure, a shape of the S/D region at an interface with the contact structure is convex.

Abstract: Disclosed herein are IC structures with nanoribbon transistors and S/D contacts at opposite sides of nanoribbons, and related methods and devices. An example IC structure includes a nanoribbon; a transistor including a channel portion in a portion of the nanoribbon, a first S/D region, and a second S/D region; a first conductive contact in conductive contact with the first S/D region, the first conductive contact being at the front side of the channel portion; a second conductive contact in conductive contact with the second S/D region, the second conductive contact being at the back side of the channel portion; and an insulator structure in contact with the first S/D region, the insulator structure being at the back side of the channel portion, where, in a cross-sectional side view of the IC structure, a shape of the insulator structure at an interface with the first S/D region is convex.

Abstract: Methods, apparatus, and systems are disclosed for approximating numerical computations in deep neural networks. An example apparatus includes at least one memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to generate a lookup table based on input elements, index the lookup table using tensor values, the tensor values associated with an output index, and output a vector in destination numeric format based on the lookup table, the vector including output values in a floating-point representation.

Abstract: Disclosed herein are embodiments of a waveguide structure, comprising: a deep rib waveguide on a slab and a plurality of shallow rib waveguides on the slab. The deep rib waveguide has a first etch-depth, the plurality of shallow rib waveguides has a second etch-depth, and the first etch-depth is greater than the second etch-depth.

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

Abstract: Examples described herein relate to a network interface device that includes circuitry and a memory. In some examples, the circuitry is to perform image construction operations, wherein the image construction operations comprise access to a base image of an application from the memory in the network interface device. In some examples, the circuitry is to provide a host server access to a constructed image bundle of the application.