Patents Assigned to Intel Corporation (INTEL)
  • Publication number: 20260247953
    Abstract: Techniques are provided herein to form an integrated circuit having backside conductive contacts beneath gate structures. Backside cavities beneath the gate structures are formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a subfin region that is also removed using a backside etch and replaced with a dielectric material. Suitable lithographic operations may be performed on the backside dielectric material along with an anisotropic etch to form any number of cavities through the dielectric material. The backside conductive contacts are then formed within the backside cavities.
    Type: Application
    Filed: February 19, 2025
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Shaun Mills, Joseph D'Silva, Mauro J. Kobrinsky
  • Publication number: 20260245167
    Abstract: Systems and methods are provided for a hybrid image processing system that integrates latent diffusion model outputs into a hardware ISP pipeline through floating latent space projection operators. The system includes a latent projector that maps ISP image data into the latent space of a diffusion model, a latent merge block that combines the projected image representation with the diffusion model's output in the latent space, and a latent deprojector that converts the merged representation back to the image domain. The latent projector and deprojector are compact convolutional neural networks trained to approximate the variational autoencoder encoder and decoder of the diffusion model. Real-time operation is enabled through latent-domain computation, temporal subsampling of the diffusion model with latent-space interpolation, and static background masking. The system enables incorporation of AI-generated content into live video with high fidelity and temporal coherence.
    Type: Application
    Filed: April 8, 2026
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Noam Levy, Dor Barber
  • Publication number: 20260246577
    Abstract: This disclosure describes systems, methods, and devices related to resource unit tone allocations. A device may identify null tones and first direct current tones of a bandwidth, the bandwidth including resource units of tones; generate, using the null tones and the first direct current tones, data tones for a 26-tone resource unit, pilot tones for the 26-tone resource unit, and second direct current tones for the 26-tone resource unit; cause transmission, to a second wireless device, of a first frame including an indication that the 26-tone resource unit is allocated to the second wireless device; and identify a second frame received from the second wireless device using the 26-tone resource unit.
    Type: Application
    Filed: June 28, 2022
    Publication date: August 20, 2026
    Applicant: INTEL CORPORATION
    Inventors: Juan FANG, Xiaogang CHEN
  • Publication number: 20260246739
    Abstract: Examples described herein relate to a network interface device. In some examples, packet processing circuitry in the network interface device is to receive a first packet and based on the first packet being associated with an identifier for which an entry is not present in a look-up table accessible to the packet processing circuitry, the packet processing circuitry is to provide the identifier for the first packet and an action for the identifier of the first packet and cause the first packet to configure a second look-up-table accessible to the packet processing circuitry with the action for the identifier.
    Type: Application
    Filed: November 13, 2025
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Anjali Singhai JAIN, Nupur JAIN, Elazar COHEN, John Andrew FINGERHUT, Neha SINGH, Vinoth Kumar CHANDRA MOHAN, Alana SWEAT, Arunkumar BALAKRISHNAN
  • Publication number: 20260247379
    Abstract: The disclosure is directed to systems and methods for multicast and broadcast services (MBS) for a wireless network including transmitting to a user equipment (UE) a signaling configuration for reception by the UE of multicast and broadcast services (MBS) in a low quality of service (QoS) multicast or broadcast delivery using an multicast control channel (MCCH) carried over a physical downlink shared channel (PDSCH) scheduled by a downlink control information (DCI) holding a cyclic redundancy check (CRC) scrambled with a dedicated radio network temporary identifier (RNTI) identifying the low QoS or broadcast reception capability of the UE. The method includes monitoring by the UE a physical downlink control channel (PDCCH) cell specific search space (CSS) configured for MBS for the DCI scheduling, the PDSCH carrying the MCCH in the DCI.
    Type: Application
    Filed: April 7, 2026
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Avik SENGUPTA, Debdeep CHATTERJEE
  • Publication number: 20260244906
    Abstract: The application relates to a memory access adaptive self-attention mechanism for a Transformer model. A method may include: estimating first execution time of selecting a number k of dominant data elements from an initial self-attention input matrix for a Transformer model to generate a sparse self-attention input matrix; estimating second execution time of performing a self-attention operation for the Transformer model based on the sparse self-attention input matrix; estimating third execution time of performing the self-attention operation based on the initial self-attention input matrix; and performing the self-attention operation based on the first execution time, the second execution time and the third execution time.
    Type: Application
    Filed: October 28, 2022
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Ganmei YOU, Li XU
  • Publication number: 20260245299
    Abstract: An apparatus and method for shader thread optimizations. For example, a graphics processing apparatus comprises: one or more graphics processing cores to execute hull shaders to configure tessellation operations to be performed on one or more input meshes; tessellation circuitry to tessellate the one or more input meshes to generate a plurality of minimally tessellated patches and a plurality of non-minimally tessellated patches according to a tessellation function; and domain shader circuitry to buffer domain points corresponding one or more of the minimally tessellated patches until a sufficient number of domain points are buffered to maximize or improve utilization on the one or more graphics cores.
    Type: Application
    Filed: February 19, 2025
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Amandeep SINGH, Abhinav SRIVASTAVA, Arthur HUNTER, FNU AMAN, Swapnil Shashank Gautam
  • Publication number: 20260247965
    Abstract: Techniques are provided herein to form semiconductor dies (or integrated circuits) with a thermally conductive layer adjacent to a bond interface to enhance the thermal dissipation from the semiconductor devices. A semiconductor die or integrated circuit includes any number of semiconductor devices within a device layer. A frontside interconnect region is provided above the device layer to, for example, route signals between the various semiconductor devices in the device layer. A thermally conductive layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive layer includes a material having a thermal conductivity of, for example, at least 1.5 W/m·K. A bond layer may be provided adjacent (e.g., directly above or directly below) the thermally conductive layer and may be any suitable dielectric material, such as silicon dioxide.
    Type: Application
    Filed: February 19, 2025
    Publication date: August 20, 2026
    Applicant: Intel Corporation
    Inventors: Joseph D'Silva, Mauro J. Kobrinsky, Ehren Mannebach, Shaun Mills, Lei Jiang, Edwin B. Ramayya, Colin D. Landon, Daniel Pantuso
  • Patent number: 12712555
    Abstract: The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Run Levinger, Ashoke Ravi
  • Patent number: 12713618
    Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Christopher M. Neumann, Brian Doyle, Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Uygar E. Avci, Eungnak Han, Manish Chandhok, Nafees Aminul Kabir, Gurpreet Singh
  • Patent number: 12713928
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Chee Kheong Yoon, Telesphor Kamgaing, Min Suet Lim, Kavitha Nagarajan, Chu Aun Lim
  • Patent number: 12713950
    Abstract: In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Gang Duan, Suddhasattwa Nad
  • Patent number: 12713334
    Abstract: For example, an Access Point (AP) Multi-Link Device (MLD) and/or a non-AP MLD may be configured to utilize a mechanism configured to support link disablement of an AP. For example, the AP MLD may be configured to transmit from an AP of the AP MLD a broadcast frame including a link disable advertisement, the link disable advertisement to advertise a link disablement of the AP for all non-AP MLDs associated with the AP, the link disablement of the AP to indicate that the AP is to be unavailable for communication with all the non-AP MLDs associated with the AP; and disable communication of beacon frames and response frames from the AP based on the link disable advertisement.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 18, 2026
    Assignee: INTEL CORPORATION
    Inventor: Laurent Cariou
  • Patent number: 12713388
    Abstract: This disclosure describes systems, methods, and devices related to performance measurements. A device may decode a management service (MnS) service request received from an MnS consumer for the 5G system (5GS), wherein the service request is associated with a performance measurement collection service to be delivered by the service producer to the consumer related to a location management function (LMF). The device may detect performance measurements data received from the LMF. The device may decode from the performance measurements data a measurement label associated with the performance measurements data based on the MnS service. The device may encode a service response based on the performance measurements data received from the PCF.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Yizhi Yao, Joey Chou
  • Patent number: 12711690
    Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
    Type: Grant
    Filed: October 15, 2024
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Gabor Liktor, Karthik Vaidyanathan, Jefferson Amstutz, Atsuo Kuwahara, Michael Doyle, Travis Schluessler
  • Patent number: 12713536
    Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Aleksandar Aleksov, Feras Eid, Henning Braunisch, Thomas L. Sounart, Johanna Swan, Beomseok Choi, Krishna Bharath, William J. Lambert, Kaladhar Radhakrishnan
  • Patent number: 12713440
    Abstract: An apparatus and system are described to provide carrier switching rules for multiple aperiodic Sounding Reference Signals (SRS) resource sets triggered by a single downlink control information (DCI). Whether the user equipment (UE) retunes between a source component carrier (CC) and a target CC for an SRS transmission is dependent on a time period between adjacent SRS resource sets in addition to priorities of the SRS transmission on the target CC and a simultaneous transmission on the source CC. In addition, timing of another DCI scheduling the simultaneous transmission received prior to the associated SRS transmission affects which of the simultaneous transmission or the associated SRS transmission is transmitted.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Guotong Wang, Alexei Davydov
  • Patent number: 12713058
    Abstract: An embodiment of an adaptive video encoder may include technology to determine headset-related information including at least one of focus-related information and motion-related information, and determine one or more video encode parameters based on the headset-related information. The adaptive video encoder may also encode a macroblock of a video image based on the one or more determined video encode parameters. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: May 19, 2025
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: YunBiao Lin, Changliang Wang, Ce Wang, Yongfa Zhou, Bo Zhao, Ping Liu, Jianwei Yang, Zhan Lou, Yu Yang, Yating Wang, Wenyi Tang, Bo Qiu
  • Patent number: 12710913
    Abstract: A system may receive information from a system under test, such as an automotive system under test, and capture multiple display streams from the system under test. The display streams may be processed and composited using virtual serializer/deserializer (virtual SerDes) operations that combine the multiple streams into a single super-frame format. The composited stream is then encoded and broadcast. The system may enable multiple users to simultaneously access and interact with the display streams remotely, with the virtual SerDes operations supporting numerous logical displays for software development and validation. The system may provide synchronized display viewing and allows dynamic switching between multi-display tiled views and single display views while preserving spatial and interleaved super-frame formats.
    Type: Grant
    Filed: December 20, 2024
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Christopher J. Cormack, Adam T. Lake
  • Patent number: 12710788
    Abstract: A lid controller hub (LCH) comprising processing components located in the lid of a mobile computing device, such as a laptop, processes sensor data generated by input sensors (microphones, cameras, touchscreen) and provides for improved and enhanced experiences over existing devices. For example, the LCH provides hardened privacy and the synchronization of touch display activities with the display refresh rate, the latter providing for a smoother and more responsive touch experience over existing designs. The LCH comprises neural network accelerators and digital signal processors that enable waking a device upon detection of an authenticated user's voice or face. The LCH also allows for video- and audio-based contextual awareness and adaptive cooling. By enabling a reduced hinge wire count and a typical day's usage with a single battery charge, an LCH can also provide for an improved industrial design to a simpler hinge and smaller battery.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: August 18, 2026
    Assignee: Intel Corporation
    Inventors: Marko Bartscherer, Aleksander Magi, Paul S. Diefenbaugh, Prashant Dewan, Kristoffer Fleming, Kathy Bui, Russell Beauregard, Abin Thomas