Patents Assigned to Intel Corporation
  • Patent number: 9152596
    Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Su Wei Lim
  • Patent number: 9154251
    Abstract: Embodiments herein describe apparatuses, systems, and methods for signaling to support downlink coordinated multipoint (CoMP) communications with a user equipment (UE) in a wireless communication network. In embodiments, the UE may be configured with a plurality of channel state information (CSI) processes (e.g., via radio resource control (RRC) signaling) to use for providing CSI feedback to an evolved Node B (eNB) to support downlink CoMP communications. The UE may be configured with a plurality of sets of CSI processes. The UE may further receive a downlink control information (DCI) message from the eNB that indicates one of the configured sets of CSI processes on which the UE is to provide CSI feedback to the UE. The UE may generate the CSI feedback for the indicated set of CSI processes, and transmit the CSI feedback to the eNB in a CSI report.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Kamran Etemad, Alexei Davydov
  • Patent number: 9154279
    Abstract: Disclosed embodiments may include an apparatus having one or more processors coupled to one or more computer-readable storage media. The one or more processors may be configured to transmit and/or receive channel state information reference signal (CSI-RS) resource configuration information, demodulation reference signals (DM-RS), uplink sounding reference signals (SRS), and power control parameters to support uplink coordinated multi-point (CoMP) operations. Other embodiments may be disclosed.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Debdeep Chatterjee, Kamran Etemad, Rongzhen Yang, Jong-Kae Fwu, Apostolos Papathanassiou
  • Patent number: 9153671
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • Patent number: 9153201
    Abstract: A method and system for producing an image to be displayed are disclosed herein. The image includes a plurality of pixels. An example of the method includes dedicating a fixed amount of memory to store a data structure for a pixel of plurality of pixels. The method also includes building a visibility function and determining a partial color sum for each fragment of the plurality of fragments. A pixel color is determined using the visibility function and the partial color sums.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventor: Marco Salvi
  • Patent number: 9154267
    Abstract: Technology for device discovery using a device-to-device (D2D) sounding reference signal (SRS) and device discovery using D2D SRS in a channel measurement group (CMG) is disclosed. In an example, a user equipment (UE) configured for device discovery via a node using the D2D SRS can include a transceiver module. The transceiver module can send a radio resource control (RRC) device discovery request to a node, scan D2D SRS subframes of proximity UEs using D2D SRS triggering, and send feedback to the node of detected D2D SRS information of the proximity UEs. The proximity UE can be located within a same cell as the UE.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventors: Hong He, Seunghee Han, Youn Hyoung Heo, Jong-Kae Fwu, Hyung-Nam Choi, Mo-Han Fong, Yujian Zhang, Umesh Phuyal, Rongzhen Yang, Feng Chen, Hujun Yin, Xiaogang Chen
  • Patent number: 9152473
    Abstract: Methods and apparatus relating to table driven multiple passive trip, platform passive thermal management are described. In one embodiment, the power consumption limit of one or more components of a platform is modified based on one or more thermal relationships between one or more power consuming components of the platform and one or more heat generating components of the platform. Furthermore, a first relationship of the one or more thermal relationships indicates a mapping between a plurality of temperature thresholds and a corresponding plurality of performance limits. Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: James G. Hermerding, II, Ramya Subramanian, Vasudevan Srinivasan
  • Patent number: 9152417
    Abstract: Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Cheng Wang, Youfeng Wu
  • Patent number: 9152183
    Abstract: In one embodiment a locking mechanism for a hinge, comprises a housing defining a chamber which is to contain a magnetorheological (MR) fluid, a bias mechanism which disposed at a first end of the chamber, a piston disposed at a second end of the chamber, the piston to be coupled to a hinge rotatable about a first axis, wherein rotation of the hinge about the first axis translates the piston laterally in the housing on a first side of the chamber, and a magnet positioned proximate the housing to change the MR fluid from a first state in which the MR fluid exhibits a low viscosity to a second state in which the MR exhibits a high viscosity. Other embodiments may be described.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventor: Nicolas A. Kurczewski
  • Patent number: 9152382
    Abstract: In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Brian J. Hickmann, Dennis R. Bradford, Thomas D. Fletcher
  • Patent number: 9152306
    Abstract: Various embodiments are generally directed a method and apparatus having a touch screen module to receive first input data from a touch screen sensor based on one or more detected touch inputs at a first location of a virtual object displayed on a display. In addition, an ultrasonic module may receive second input data from an ultrasonic sensor based on detected non-touch motion associated with the virtual object. The detected non-touch motion may be tracked from the first location to a second location in a direction away from the first location based on the second input data and used to determine the second location for the virtual object based on the tracking.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventors: Glen J. Anderson, Albert Yosher, Anthony L. Chun
  • Patent number: 9152561
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 9152257
    Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: James A. McCall, Kuljit S. Bains, Derek M. Conrow, Aaron Martin
  • Patent number: 9154157
    Abstract: Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data. The search unit may use a look-up table to identify appropriate compression or decompression symbols. The look-up table may be populated with a table derived using the variable length coding symbols of a sequence of vertices to be compressed or extracted from a received data stream to be decompressed. A comparator and a finite state machine may be implemented in the search unit to facilitate traversal of the look-up table.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Nadathur Rajagopalan Satish, Changkyu Kim, Jatin Chhugani
  • Patent number: 9153064
    Abstract: A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Ganesh S. Dasika, Mikhail Smelyanskiy, Jose Gonzalez, Changkyu Kim, Jatin Chhugani, Yen-Kuang Chen, Julio Gago, Santiago Galan, Victor Moya Del Barrio
  • Patent number: 9153008
    Abstract: In accordance with some embodiments, caching may be improved for tiles on shared edges between triangles. In some embodiments, the technique may be used for either color and depth caches or both caches.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Jim K. Nilsson
  • Patent number: 9155088
    Abstract: A system and method for aggregating subscriber information at a delivery edge is disclosed. The method comprises interfacing a user profile aggregation device (UPAD) at a subscriber location with at least one subscriber database in each of a wired network core and a wireless network core. The wired network core and the wireless network core are operated by a Multi-System network Operator. Profile information can be aggregated at the UPAD about the subscriber from at least one database in the wired network core and the wireless network core. The subscriber's aggregated profile information can be communicated to the MSO.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventors: Ashok Sunder Rajan, Puneet K. Jain
  • Patent number: 9153552
    Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Deepak Kulkarni, Chia-Pin Chiu, Tannaz Harirchian, John S. Guzek
  • Patent number: 9152663
    Abstract: Systems and methods may determine a boundary value data unit in a large data set in parallel with determining an associated index of the determined boundary value data unit into the large data set using a single instruction multiple data (SIMD) instruction set architecture and a specialized data layout of array entries. In one example, the specialized data layout of array entries combines a data value and its associated index to an array into a single array entry.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Li-An Tang, Shih-Hsuan Hsu
  • Patent number: 9152022
    Abstract: Techniques are disclosed for compensating for deficiencies of a given image projector so as to eliminate or otherwise reduce discrepancies between original image data provided to the projector and the actual image projected by the projector. The techniques also may be used to enhance an attribute of the original image data to improve the image projected by the projector. The techniques can be implemented, for instance, with an imaging capture device and an image comparison engine. In operation, the imaging capture device can capture a projected image from a viewing surface, and the image comparison engine can compare the original image data with the projected image captured by the imaging capture device. Based on the results of this comparison, an adjustment then can be made to achieve the desired projected image. The adjustment may entail, for example, adjusting the original image data provided to the projector and/or adjusting projector settings.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: October 6, 2015
    Assignee: INTEL CORPORATION
    Inventor: Michael Stahl