Patents Assigned to Intel Corporation
  • Shader serialization and instance unrolling
    Patent number: 9123167
    Abstract: A graphics engine with shader unit thread serializing and instance unrolling functionality that executes multi-threaded shader logic in a single hardware thread is described. Hardware accelerated tessellation functionality is implemented utilizing programmable pipeline stages that allow custom, runtime configuration of graphics hardware utilizing programs compiled from a high level shader language that are executed using one or more shader execution cores. In one embodiment, multiple shader unit program threads are serialized to run in one hardware thread to allow a greater number of instructions to be executed on the shader cores and preserve hardware threads for primitive processing by other shader units.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Yunjiu Li, Michael Green
  • Method and apparatus for three-dimensional tracking of infra-red beacons
    Patent number: 9122945
    Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: David J. Cowperthwaite, Bradford H. Needham
  • Electroless filled conductive structures
    Patent number: 9123706
    Abstract: Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 1, 2015
    Assignee: INTEL CORPORATION
    Inventors: Daniel J. Zierath, Shaestagir Chowdhury, Chi-Hwa Tsang
  • Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode
    Patent number: 9122464
    Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Efraim Rotem, Alon Naveh, Sanjeev S. Jahagirdar, Varghese George
  • Location-aware mobile application management
    Patent number: 9125000
    Abstract: Described herein are techniques related to managing mobile applications (“apps”) of a mobile device based, at least in part, upon the determined location of the device. The techniques described herein are especially suited for situations where the present location differs from the locations associated with particular apps that are already installed on the mobile device. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Anthony G. LaMarca, Kirk W. Skeba, Jaroslaw J. Sydir
  • Handling wait time in a congested wireless communication network
    Patent number: 9125103
    Abstract: Embodiments of the present disclosure describe techniques and configurations for handling a wait time in a wireless communication network when the network is determined to be congested. An apparatus may include computer-readable media having instructions and one or more processors coupled with the computer-readable media and configured to execute the instructions to send a radio resource control request message to a wireless network controller, receive a response message including an extended wait time value, determine upon receipt of the response message whether a back-off timer associated with the apparatus is running, and determine whether to start the backoff timer with the received extended wait time value based at least in part on the determination of whether the back-off timer is running and the received wait time value is integrity protected.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventor: Vivek Gupta
  • Charge injection and drain-based electrical overstress (EOS) protection apparatus and method
    Patent number: 9124084
    Abstract: An electrical overstress (EOS) protection circuit that at least partially neutralizes or compensates for undershoot and overshoot in first and second signals that are communicated using differential signaling, such as with USB communications. For an undershoot, the EOS protection circuit injects charge into pads that receive the first and second signals. For an overshoot, the EOS protection circuit drains charge from the pad that receives the second signal and injects charge into the pad that receives the first signal.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: September 1, 2015
    Assignee: INTEL CORPORATION
    Inventor: Suhas Vishwasrao Shinde
  • Method and apparatus for supporting image processing, and computer-readable recording medium for executing the method
    Patent number: 9124814
    Abstract: A support for image processing is provided, comprising: (a) detecting respective face regions from images consecutively photographed for a first person at predetermined time intervals by an image pickup unit to display images of the face regions detected in relation to the first person in a first region of a screen, and providing a user interface for indicating that a specific face image is selected from the face images of the first person displayed in the first region; (b) additionally displaying the specific face image through a second region adjacent to the first region; and (c) displaying a synthesized image using the specific face image as a representative face of the first person, when the specific face image displayed through the second region is selected.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Daesung Kim, Jaihyun Ahn
  • Network congestion management
    Patent number: 9124503
    Abstract: Technologies for managing congestion of a communication channel includes a network device for receiving a network packet from a computing device destined for another computing device, analyzing network traffic flows over a communication channel established between the network device and an upstream network device, and determining whether the communication channel is congested as a function of the network traffic flows. Such technologies may also include storing the received packet in a local storage in response to determining that the communication channel is congested, transmitting an acknowledgement packet to the computing device in response to storing the received network packet local storage, and transmitting the stored network packet to the upstream network device in response to determining that the communication channel is no longer congested.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sanjay Rungta, Dileep K. Basam
  • Common idle state, active state and credit management for an interface
    Patent number: 9122815
    Abstract: In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Rohit R. Verma
  • Memory controller for reducing capacitive coupling in a cross-point memory
    Patent number: 9123410
    Abstract: The present disclosure relates to a memory controller. The memory controller may include a memory controller module configured to identify a target word line in response to a memory access request, the target word line included in a cross-point memory, the memory controller module further configured to perform a memory access operation on a memory cell of the cross-point memory, the memory cell coupled between the target word line and a bit line; and a word line control module configured to float at least one adjacent word line adjacent the target word line, the floating comprising decoupling the at least one adjacent word line from at least one of a first voltage source or a second voltage source. In some embodiments, the floating reduces an effective capacitance associated with the target word line during the memory access operation.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Hernan A. Castro, Jeremy M. Hirst, Eric Carman
  • Verified sensor data processing
    Patent number: 9124635
    Abstract: Sensor data may be filtered in a secure environment. The filtering may limit distribution of the sensor data. Filtering may modify the sensor data, for example, to prevent identification of a person depicted in a captured image or to prevent acquiring a user's precise location. Filtering may also add or require other data use controls to access the data. Attestation that a filter policy is being applied and working properly or not may be provided as well.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Scott H. Robinson, Jason Martin, Howard C. Herbert, Michael LeMay, Karanvir Ken S. Grewal, Keith L. Shippy, Geoffrey Strongin
  • Methods of forming secured metal gate antifuse structures
    Patent number: 9123724
    Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
  • CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
    Patent number: 9123567
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Instruction for shifting bits left with pulling ones into less significant bits
    Patent number: 9122475
    Abstract: A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Igor Ermolaev, Andrey Naraikin, Robert Valentine
  • Remote audio
    Patent number: 9124441
    Abstract: Various embodiments for remote presentation of an interface of a computing device, such as a PC, are described herein. In particular, in various illustrated embodiments, a local device such as a Digital Media Adapter (DMA), mobile device, cellular telephone, etc. may be used to receive input from a remote control, where the local device provides human perceptible feedback, such as a sound, visual response, etc., responsive to use of the remote control. In some embodiments, the local device may contain a memory or cache for locally storing particular feedback data for human perceptible feedback. In various embodiments, a communication protocol is provided for storing, triggering, deleting, etc. feedback data in the memory or cache. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Ylian Saint-Hilaire, Bryan Y. Roe, Nelson F. Kidd
  • Flexibly integrating endpoint logic into varied platforms
    Patent number: 9122811
    Abstract: In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Michael Klinglesmith, Mohan Nair, Joseph Murray
  • Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
    Patent number: 9123790
    Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Han Wui Then, Marko Radosavljevic
  • Data prioritization, storage and protection in a vehicular communication system
    Patent number: 9124421
    Abstract: This disclosure is directed to data prioritization, storage and protection in a vehicular communication system. A black box (BB) in a vehicle may receive data from an on-board unit (OBU) and a vehicular control architecture (VCA). The OBU may interact with at least one RSU that is part of an intelligent transportation system (ITS) via at least two channels, at least one of the at least two channels being reserved for high priority messages. The OBU may transmit ITS data to the BB via a secure communication channel, which may be stored along with vehicular data received from the VCA in encrypted form. In response to a request for data, the BB may authenticate a requesting party, determine at least part of the stored data to which the authenticated party is allowed and sign the at least part of the stored data before providing it to the authenticated party.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Meiyuan Zhao, Christian Maciocco, Shilpa Talwar, Jessie Walker
  • Near field communications (NFC) coil with embedded wireless antenna
    Patent number: 9125007
    Abstract: Described herein are techniques related to near field coupling and WLAN dual-band operations. For example, a WLAN dual-band utilizes the same coil antenna that is utilized for near field communications (NFC) functions. The WLAN dual-band may be integrated into an NFC module to form a single module.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang