Abstract: A computer system may comprise a receiver to perform equalization. The receiver comprises an equalizer. The equalizer may determine locations of a principal tap, a platform noise tap, and a pre-cursor tap in a feedforward path of an equalizer. Also, the equalizer may determine locations of a post-cursor tap, a cross-term tap, and a portable tap in a feedback path of the equalizer. The receiver may align the portable tap in the feedback path with the principal tap in the feedforward path. The platform noise tap may cancel the effect of platform noise on a principal located at the principal tap, thus enabling the computer system to operate effectively in severe platform noise environment. Also, the computer system may operate in statics and portable environment in which platform noise and AGWN may be present.
Type:
Grant
Filed:
June 30, 2009
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Ernest Tsui, Siva Simanapalli, Lei Shao
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.
Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
Type:
Grant
Filed:
December 22, 2005
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Mark Rowland, Ganapati Srinivasa
Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.
Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.
Type:
Grant
Filed:
November 18, 2008
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Seh W. Kwa, Michael Calyer, Ravi Ranganathan, Narayan Biswal
Abstract: A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread.
Abstract: A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
Type:
Grant
Filed:
September 10, 2009
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Sivakumar Radhakrishnan, Sin S. Tan, Stephan J. Jourdan, Lily P. Looi, Yi-Feng Liu
Abstract: In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.
Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
Abstract: Embodiments of the invention provide devices and methods for extracting nucleic acid molecules from solution using electric fields. The structures and methods of embodiments of the invention are suited to incorporation into micro and nano fluidic devices, such as lab-on-a-chip devices and micro total analysis systems.
Type:
Grant
Filed:
October 14, 2011
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Steven A. Sundberg, Xing Su, Grace Credo
Abstract: Methods and systems to balance the load among a set of processing units, such as servers, in a manner that allows the servers periods of low power consumption. This allows energy efficient operation of the set of processing units. Moreover, the process is adaptable to variations in systemic response times, so that systemic response times may be improved when operational conditions so dictate.
Abstract: A flow tube apparatus may include a flow tube having a first opening and a second opening, a corona electrode provided in the flow tube, a collecting electrode provided in the flow tube, and at least one focusing electrode provided in the flow tube to guide ions and thereby provide an ionic wind. In at least one embodiment, the flow tube apparatus may be provided in an electronic apparatus to provide an air flow.
Type:
Grant
Filed:
December 24, 2009
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Mark MacDonald, Rajiv K. Mongia, David B. Go
Abstract: Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of a plurality of active threads in a multiprocessor system that includes memory livelock breaker logic and/or starvation avoidance logic. Other embodiments are also described and claimed.
Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.
Abstract: Apparatuses, methods, systems, and computer program products to process QoS packets of wireless traffic without explicit control negotiations are disclosed. An embodiment may comprise a mobile computing device with wireless communications capabilities. The mobile computing device may be a client that associates or connects with an access point or communicates another client device, such as a peripheral device with wireless capabilities. The mobile computing device may monitor wireless packet traffic being transmitted from the mobile computing device. For example, the mobile computing device may monitor the packets being transmitted from a video streaming application to the peripheral device, which may comprise an LCD monitor that has wireless communications capabilities. The mobile computing device may mark the packets of the video stream as QoS packets even though the video streaming application may not do so, and place the marked packets in a QoS queue for priority processing.
Abstract: A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.
Abstract: Devices, methods, and software program products for reverse execution of a simulation and/or tracing a value are provided. A state of a preceding checkpoint may be restored and a simulation may be run forward. Break points or watch points may be noted and the state of the last occurring breakpoint or watch point preceding the current simulation position may be restored. If no breakpoint or watch point occurred, an earlier checkpoint may be loaded and the previous steps may be repeated.
Type:
Grant
Filed:
November 8, 2010
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Samuel Rydh, Peter S. Magnusson, Bengt Werner
Abstract: An improved handover process is described for a cellular wireless network. In one example, a method includes registering a mobile station to a first base station and a first gateway, handing the mobile station over to a second base station coupled to the first gateway, selecting a second gateway coupled to the mobile station, registering the mobile station to the second gateway, de-registering the mobile station from the first gateway, and handing the mobile station over to a third base station coupled to the second gateway and not coupled to the first gateway.
Abstract: Methods and systems to determine channel frequency responses corresponding to multi-carrier signals, such as OFDM signals, including to filter or mask noise from channel frequency response estimates in a time domain.
Type:
Grant
Filed:
December 19, 2008
Date of Patent:
September 25, 2012
Assignee:
Intel Corporation
Inventors:
Thushara Hewavithana, Bernard Arambepola, Parveen K. Shukla
Abstract: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to access at least one portion of data. The at least one request may indicate, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance. The at least one request may be to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets are accessed. The at least one request may be comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size.
Type:
Grant
Filed:
August 12, 2008
Date of Patent:
September 18, 2012
Assignee:
Intel Corporation
Inventors:
Steen K. Larsen, Ramakrishna Huggahalli