Abstract: A method and apparatus for modifying an events queue for extending an extended mark-up language (XML) processor's feature set are described. In one embodiment, the method includes the parsing of an XML document to generate an initial event queue. During parsing of the XML document, an event associated with a parser plug-in module may be detected. When an event associated with a parser plug-in module is detected, control is passed to the plug-in module to perform event-based functionality to modify the initial event queue to form a modified event queue. Subsequently, any additional event information contained within the modified event queue, as generated by the parser plug-in module, is reported to, for example, an end user application. Other embodiments are described and claimed.

Abstract: Various embodiments are directed to non-overlap region based automatic global alignment for ring camera image mosaic. The non-overlap region based homography calculation may be based on feature points of a planar target appearing in a non-overlap region among images captured by a multi-camera based video capture device. Other embodiments are described and claimed.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: A traditional registry, such as a global UDDI server, is not designed to accommodate transitory devices, e.g., devices that may frequently attach and detach from a network, often-times without warning, such as virtual machines offering or desiring services that are periodically instantiated and then suspended or destroyed. To accommodate such transitory devices, a dynamic resource/service registry may be implemented that leverages lower-level protocols or state to determine appropriate registry updates to keep the registry state consistent with currently-active virtual machines. For example, a virtual machine monitor (VMM) may track creation and suspension or deletion of a virtual machine (VM), and resources advertised by the VM, where the VMM appropriately adds or removes registry entries for the VM as the state of the VM changes or provides hooks (e.g. notifications) or other instrumentation based on said state or protocols to enable other associated modules or agents (e.g.

Abstract: An electronic assembly having a microelectronic die, a heat spreader and a heat sink. A first thermal interface material is disposed between the microelectronic die and the heat spreader. A second thermal interface material is disposed between the heat spreader and a heat sink. The first and second interface materials each comprising a phase change polymer, a solderable material and a plurality of thermally conductive non-fusible particles. The solderable material interconnecting the non-fusible particles to form a plurality of columnar structures within the phase change polymer.

Abstract: Narrow surface corrugated gratings for integrated optical components and their method of manufacture. An embodiment includes a grating having a width narrower than a width of the waveguide on which the grating is formed. In accordance with certain embodiments of the present invention, masked photolithography is employed to form narrowed gratings having a desired grating strength. In an embodiment, an optical cavity of a laser is formed with a reflector grating having a width narrower than a width of the waveguide. In another embodiment an integrated optical communication system includes one or more narrow surface corrugated gratings.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.

Abstract: A method and system are disclosed. In one embodiment the method includes computing, during runtime, an active hash value of a hypervisor on a computer platform using an authenticated integrity agent. The method also includes comparing the active hash value to a registered hash reference value. The method also includes verifying the integrity of the hypervisor when the active hash value and the registered hash reference value match.

Abstract: An electronic device comprises a housing, at least one heat generating component in the housing, and at least one thermal management device in thermal communication with the at least one heat generating component, wherein the at least one thermal management device selectively allocates heat flow to one or more portions of the housing. Other embodiments may be described.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed.

Abstract: One or more accelerometers may be coupled to a radio frequency identification (RFID) tag, so that the response of the RFID tag indicates the acceleration being sensed by the accelerometer(s). In some embodiments the accelerometers may be powered from the RF energy harvested by the RFID tag from a received RF signal. The sensed acceleration indicated in the response may be used to determine a motion and/or an orientation of an object coupled to the accelerometers.

Abstract: A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

Abstract: Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Abstract: Detecting loss of stream cipher synchronization between a transmitter and a receiver in a video processing system may be achieved by receiving, by the receiver, an encrypted video frame from the transmitter, obtaining an encrypted value for a selected pixel in the encrypted video frame, decrypting the encrypted pixel value using a first portion of the receiver's current key stream, re-encrypting the pixel value using a second portion of the receiver's current key stream, sending the re-encrypted pixel value from the receiver to the transmitter, obtaining, by the transmitter, a plaintext value for the selected pixel from a corresponding original video frame and encrypting the plaintext pixel value using a second portion of the transmitter's current key stream, and comparing the re-encrypted pixel value received from the receiver with the encrypted pixel value generated by the transmitter and detecting a loss of cipher synchronization when the values do not match.

Abstract: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy.

Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken.

Abstract: Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a plurality of signals corresponding to write pointers of a buffer and a read pointer of the buffer are generated. The signals corresponding to the write pointers of the buffer are to be generated based on different data patterns for transmission over different channels. Other embodiments are also claimed and described.

Abstract: In one embodiment, the present invention includes a method for selecting first data received in a first die of a multi-chip package (MCP) from a second die of the MCP via an intra-package link for output from a selector during a first clock period of a first clock signal, selecting second data transmitted from the second die to the first die for output from the selector during a second clock period, and transmitting the first and second data from the MCP via an external link. Other embodiments are described and claimed.

Abstract: In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.