Patents Assigned to Intel Corporation
  • Patent number: 7467104
    Abstract: A digital content pricing apparatus may include a sales computer and a memory used to retain digital content items associated with a base price and one or more option prices, along with a final price related to the base and option prices by a final pricing formula. A method may include selecting a digital content item and at least one configuration option associated with the item, calculating the item price using appropriate adjustment factors, and calculating the final price using a final pricing formula. Pricing information, in the form of prices, adjustment factors, and formulae may be defined in meta-data descriptors included in the digital content.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Todd A. Schwartz, Bruce D. Bridges, Richard J. Qian, Vaughn S. Iverson
  • Patent number: 7465188
    Abstract: A compact PCB connector is disclosed to facilitate connection between various components of computer system. The PCB connector comprises a housing having a front side adjacent to the bottom side of the housing. A plurality of connectors supported by the housing are provided to facilitate connection between the various components of a computer system.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Beng Keat Tan, Vishva Lakshmanan, Kai Yong Cheng
  • Patent number: 7466176
    Abstract: A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Doug Huard, Robert Greiner, Anant Deval, Edward Burton
  • Patent number: 7467414
    Abstract: A system, apparatus, and method are provided for entitlement security and control. According to one embodiment, an entitlement request is received from a downstream access control system seeking entitlement permission on behalf of a user, a group of users, all users associated with the downstream access control system, or on behalf of the downstream access control system as a whole, the entitlement request is matched against entitlement rules and roles that are retrieved from a metadata repository, and the entitlement permission is granted if the entitlement request satisfies the entitlement rules and roles.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventor: David Schlesinger
  • Patent number: 7465976
    Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Matthew V. Metz, Gilbert Dewey, Ben Jin, Justin K. Brask, Suman Datta, Robert S. Chau
  • Patent number: 7466723
    Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Kersi H. Vakil, Adarsh Panikkar
  • Patent number: 7466180
    Abstract: A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventor: Darren Slawecki
  • Patent number: 7467377
    Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Li-Ling Chen
  • Patent number: 7466964
    Abstract: Wireless communication devices and methods for coordinated channel access with reduced latency in a wireless network are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventor: Lakshmipathi Sondur
  • Patent number: 7467212
    Abstract: A method of controlling a social network access control list (ACL) for a shared resource includes monitoring communications to and from a user. Social network data from the communications to and from the user is determined. An access level for the user is determined based on the social network data. The access control list is configured to provide the user the access level determined for accessing the shared resource.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Robert Adams, Jose P. Puthenkulam
  • Patent number: 7466781
    Abstract: Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Dmitry Petrov, Lev Smolyar
  • Patent number: 7467285
    Abstract: Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled by an operating system executed by the first processor. The shadow page table references at least one page in an operating system memory region accessible to processes controlled by the operating system.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, Uday Savagaonkar, Ravi Sahita, Priya Rajagopal
  • Publication number: 20080305321
    Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.
    Type: Application
    Filed: August 20, 2008
    Publication date: December 11, 2008
    Applicant: INTEL CORPORATION
    Inventors: Nachiket R. Raravikar, James C. Matayabas, JR.
  • Patent number: 7464227
    Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Sujat Jamil, David E. Miner, R. Frank O'Bleness, Steven J. Tu, Hang T. Nguyen
  • Patent number: 7464300
    Abstract: In some embodiments, a method, apparatus and system to detect and signal sequential hot plug failure diagnostics are presented. In this regard, a diagnostic agent is introduced to store a plurality of bits corresponding to a hot plug error code in a register sequentially such that a plurality of hot plug error codes can be stored in the register. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventor: Peter N. Martin
  • Patent number: 7464194
    Abstract: A method and architecture for enabling interaction between a remote device and a host computer. A service provided by the remote device is discovered, and a description pertaining to the service is retrieved by the host computer. A network communication link is the established between the remote device and the host computer based on connection information provided by the description. Host-side and client-side software service modules are run on the host and remote devices to enable interaction between the devices using a service protocol that is specific to the service. Various service protocols are provided, including a display service protocol and an input service protocol. Using commands provided by each protocol, the host computer is enabled to control the service remotely by pushing data and appropriate commands to the remote device, whereupon these commands are processed by the client-side service module to perform service operations that employ the sent data.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Ylian Saint-Hilaire, Jim W. Edwards
  • Patent number: 7463514
    Abstract: A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventor: Rezaul Haque
  • Patent number: 7464208
    Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. The semaphore control mechanism receives one or more semaphore modification requests from one or more requesting devices, identifies an ownership state of a semaphore corresponding to the one or more semaphore modification requests, arbitrates to identify modification request from a particular requesting device to succeed if the identified ownership state corresponds to the particular requesting device or if the identified ownership state corresponds to no ownership.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Steven Tu, Hang Nguyen
  • Patent number: 7463993
    Abstract: Systems and methods of thermal management provide for dynamically the upper and lower operating points of a throttled device such as a processor. In one embodiment, it is determined that the temperature of the processor is below a threshold and moving the upper operating point and the lower operating point toward one another.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Lev Finkelstein, Efraim Rotem, Oren Lamdan, Aviad Cohen
  • Patent number: 7463638
    Abstract: A network route tracing system traces a path through a network and identifiesnetwork components and communications links affected by the path. According to one embodiment of the present invention, a route is traced between two hosts in a network. The network is represented as a logical tree having a plurality of nodes. Each one of the nodes corresponds to a component in the network and each non-root node has a parent node. Two nodes are identified in the logical tree. A first node corresponds to a first host and a second node corresponding to a second host. If one of the two nodes exists at a lower level of the logical tree, then a first path is traced from the first node at the lower level to the parent node at a higher level until the parent node is at a same level of the logical tree as the second node. The first path is further traced up the logical tree from the parent node and a second path is traced up the logical tree from the second node until the first path and the second path meet at a same node.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: David M. Durham, Russell J. Fenger