Abstract: System information prompting a reconfiguration of a target device that is part of the system is received, and in response to the information, the target device is reconfigured using configuration data for the target device that has been stored in non-volatile memory of a second self-configuring device that is part of the system.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A retention mechanism for an electronic assembly which has a substrate and a heat sink. The retention mechanism includes a substrate slot that receives the substrate and a heat sink slot that receives the heat sink. There may be two retention mechanisms that are attached to a printed circuit board adjacent to an electrical connector. There may be two heat sink slots symmetrically located about the substrate slot so that the mechanism can be mounted to a left side or a right side of the connector. The symmetric slots eliminate the need for a left side mechanism and a right side mechanism. The retainer mechanism may also have a nut retainer that captures a nut that is used to attach the mechanism to the printed circuit board. The nut retainer allows the nut to be transported with the retainer mechanism during an assembly process.

Abstract: A phase change material memory cell may be formed with singulated, cup-shaped phase change material. The interior of the cup-shaped phase change material may be filled with a thermal insulating material. As a result, heat losses upwardly through the phase change material may be reduced and adhesion problems between the phase change material and the rest of the device may likewise be reduced in some embodiments. In addition, a barrier layer may be provided between the upper electrode and the remainder of the device that may reduce species incorporation from the top electrode into the phase change material, in some embodiments. Chemical mechanical planarization may be utilized to define the phase change material reducing the effects of phase change material dry etching in some embodiments.

Abstract: A method and apparatus provides increased operative life for flip-chip devices that are produced from an integrated circuit formed with electrically conductive bumps bonded to a printed circuit board substrate. The bumps and the substrate are formed from similar materials that allow control of the degree of latency for each element and produce a covalently bonded laminate structure when the bumps and substrate are brought together. The covalently bonded structure decreases bump fatigue to lengthen the operative life of the flip-chip device.

Abstract: A method and apparatus for cooling components within a computer system chassis. In one embodiment, a cooling duct unit includes an air moving unit base with an air moving unit to draw and accelerate air from outside a computer system chassis to a high velocity airflow. Connected to the air moving unit base is a duct to converge and change the high velocity airflow from a circular shape to a noncircular shape. The converged and changed high velocity airflow is directed to cool a device within a computer system chassis. As a result, the device within the computer system is chassis cooled more uniformly and efficiently, while reducing acoustic noise and providing a modular cooling duct unit design for ease of attachment and removal.

Abstract: A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

Abstract: In one embodiment, the present invention provides a radio frequency transmitter that may have a processor and a controller that reduce current consumption of the power amplifier of the radio frequency transmitter.

Abstract: A method and system analyze traffic on a network by monitoring network traffic and, when a particular network condition (for example, network congestion) is detected, gathering information about the traffic on the network by launching an agent and having the agent iteratively identify which of the links on the node on which the agent operates accepts a type or class of traffic, traverse the identified link to the node across the link, and repeat the process.

Abstract: A method and an apparatus providing an optical interconnection in an integrated circuit die. In one embodiment, an optical interconnection is used to optically interconnect a waveguide-based optical modulator through the insulating layer and back side of the semiconductor substrate of the integrated circuit die. In one embodiment, an insulating oxide layer is disposed between a semiconductor waveguide optical modulator and the back side of the semiconductor substrate. Optical conduits are disposed in the insulating oxide layer at the locations where light enters and exits the semiconductor waveguide optical modulator. In one embodiment, the optical conduits have indexes of refraction substantially equal to the indexes of refraction of the semiconductor substrate and the semiconductor waveguide optical modulator. Thus, attenuation of the light used to optically couple the semiconductor waveguide optical modulator through the back side of the semiconductor substrate is reduced.

Abstract: Heat dissipation devices and molding processes for fabricating such devices, which have at least two regions comprising different conductive materials such that efficient thermal contact is made between the different conductive materials. The molding processes include injection molding at least two differing conductive materials.

Abstract: Fragile watermarking for objects is disclosed. In one embodiment of the invention, a system includes an encoder and a decoder. The encoder encodes a watermark into a object, such as a three-dimensional object, in a fragile manner, utilizing a key. The decoder decodes the watermark from the object in which the watermark is encoded in a pubic manner, also utilizing a key. Visualization techniques for detecting alterations using fragile watermarking are also disclosed.

Abstract: A flexure and package including the same are provided. In one embodiment, the flexure is coupled to a second optical element and a substrate to maintain the second optical element in alignment with a first optical element. The flexure comprises a body, a pair of front and back legs. The attachment of the rear legs to the substrate causes the flexure to move from a first flexure position to a second flexure position, the distance between the first flexure position and the second flexure position equaling an offset distance. A specified length of the body is chosen such that the offset distance causes a second offset distance of the second optical component held by the flexure, and this second offset distance is within a specified range. The second offset distance is equal to the difference between a primary second optical component position and a secondary second optical component position.

Abstract: A circuit including a power supply plane, a ground supply plane, and a signal source that generates reference voltage signals and a first signal. The signal source includes a driver adapted to generate a first signal to the receiver, the first signal having a present and a previous voltage levels. The signal source also includes a low reference voltage generator and a high reference voltage generator, each producing a low reference voltage signal and a high reference voltage signal, respectively, from a low reference output and a high reference output, respectively. The high reference output and the low reference output are coupled to the ground plane and the power supply plane, respectively. The high reference voltage generator and the low reference generator are capable of communicating the high reference voltage signal and the low reference voltage signal to the receiver.

Abstract: A device and method to test a circuit in a chip that has memory embedded in the chip using a scan chain. This device and method generates a known signal simultaneously to a bypass circuit and the memory onboard the chip. The bypass circuit uses a series of exclusive OR gates, a flip-flop, and a multiplexer to receive the known signal. The exclusive OR gates reduce the number of signals input so that they match the number of signals output by memory. A flip-flop is used to store the data received from the exclusive OR gates and transfer it to a multiplexer. The multiplexer receives data from memory and the flip-flop and selects which data to pass on in the circuit. When a scan test is being run on the circuit the multiplexer passes on only the data from the flip-flop. When a scan test is not being run the multiplexer only passes on the data from memory.

Abstract: A timer on a microprocessor includes a vibrator formed by a comparator, a capacitor, three reference voltages, and switched current sources, which charge and discharge the capacitor. The vibrator oscillates at two different amplitudes to generate two timing windows, one at high amplitude and the other at low amplitude. A counter counts incoming clocks and times out after a fixed number of vibrator oscillations. Logic starts the timing windows and subtracts incoming clock measurements taken during the two timing windows. The logic subtraction cancels errors accumulated from the multiple ramps of the capacitor in the vibrator. The subtraction allows more precise measurement of incoming clocks. If the clocks counted exceed a threshold value, the microprocessor shuts down due to over clocking.

Abstract: A package for optical components and a method for making the package are disclosed. The package comprises a quasi-planar substrate having a positioning floor, a platform and an optional ring frame of precisely determined height. Optical components picked and placed on a substrate floor, a raised platform and frame. A flexure assembly allows fine positioning of components requiring critical optical alignment.

Abstract: An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.

Abstract: A cluster operating in accordance with an integrating operating system independent power management with operating system directed power management includes a group of hosts connected together by a cluster interconnection fabric. A cluster administrator is connected to the group of hosts via the fabric and the cluster administrator includes a cluster power manager. A group of input/output units are connected to the group of hosts and the cluster interconnection fabric. Each of the hosts includes a controller element and an operating system power manager and input/output controller device driver stack. The cluster administrator transmits a request to the controller element of one of the hosts via the fabric and receives a reply therefrom and transmits a command. The controller element transmits the command to the operating system power manager and the input/output controller device driver stack of its host and transmits a command completion acknowledgment to the cluster power manager.

Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.