Abstract: A method and apparatus for encoding a purpose into a digital signature, where purpose and digital signature bound into an extended digital signature. The extended digital signature capability binds a purpose description identifying the purpose for the digital signature so that when affixed to a digital signature, the digital signature cannot be employed for improper purposes. A hash function is used to generate a hash value from the purpose description. The hash value is used in a digital signature function to bind the purpose to a digital signature. The extended digital signature can be verified for validity by comparing it to a hash value. In an electronic transaction, the extended digital signature can allow a purpose to be bound with the digital signature so that improper or unauthorized transactions are detected and disallowed.

Abstract: A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.

Abstract: A method and an apparatus utilizing mux scan flip-flops to test for timing-related defects. In one embodiment, a delay circuit is used to act as a buffer for a scan enable signal received by the mux scan flip-flops of a test circuit. The scan mode signal is first sent to the delay circuit, which then distributes the scan mode signal to the mux scan flip-flops. Since each delay circuit can serve as the buffer for numerous mux scan flip-flops, the scan mode signal may be sent initially to a smaller number of delay circuits instead of the thousands of mux scan flip-flops that may be distributed throughout the entire integrated circuit. Furthermore, in one embodiment the delay circuit delays propagation of active-to-inactive transitions of the scan enable signal by one clock cycle, synchronizing the system clock cycle with the active-to-inactive transitions of the scan mode signal. In one embodiment, inactive-to-active transitions of the scan enable signal are propagated without the one clock cycle delay.

Abstract: A technique for improving across field dimensional control in a microlithography tool. In a lithography imaging process in which a pattern on a mask is projected to form latent images in a photosensitive medium, the critical dimension distribution across the imaging field varies due to scattering and other factors. An optical compensator having gradient neutral density filter properties is used to reduce the intensity of light at those locations corresponding to regions of an imaging field having higher exposure dose. By reducing the intensity of light at the higher dose regions, the overall dose profile is made more uniform, which reduces linewidth variations when devices are fabricated on an semiconductor wafer.

Abstract: A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of transmitting coded data signals over a bus having a limited bandwidth includes: transmitting a first edge of a data pulse and transmitting a second edge of the data pulse. The time period between the transmitted first edge and the transmitted second edge approximates one of a set of different predetermined time periods. Selected different predetermined time periods of the set of different predetermined time periods respectively correspond to unique pluralities of binary digital signals.Briefly, in accordance with another embodiment of the invention, a system comprises a first device, a second device and a bandlimited bus coupling the first device with the second device. At least one of the devices includes the capability to code data signals for transfer over the bus and at least the other device includes the capability to decode the data signals.

Abstract: A method and apparatus for testing a circuit board is disclosed. An apparatus having at least one clock source for providing a circuit board with a clock signal at a dynamically selected frequency, a storage medium storing programming instructions to control the clock source(s) to provide the clock signal at the dynamically selected frequency including a frequency that exceeds the specified operating range of frequencies for the circuit board, and for implementing parametric testing of the circuit board, and an execution unit coupled to the clock source and to the storage medium for executing the programming instructions. The programming instructions for implementing the parametric testing of the circuit board include instructions for testing the circuit board while the circuit board is supplied with the clock signal at the frequency that exceeds the operating frequency of the circuit board, thereby stressing the circuit board.

Abstract: A microprocessor that includes first and second Instruction Fetch Units (IFU) coupled therebetween is provided. The first IFU implements a first Instruction Set Architecture (ISA). The second IFU implements a second ISA. The microprocessor further includes a shared branch prediction unit coupled to the first and second IFU. The shared branch prediction unit stores prediction-related information. In the same paragraph, the present invention also provides a method of performing branch prediction. According to this method, an instruction pointer is provided to a branch prediction unit that stores information shared by first and second IFU. The instruction pointer is generated by one of the first and second IFU that is active. Determination is made of whether an instruction corresponding to the instruction pointer, provided to the branch prediction unit, is a branch instruction, and if so, it is determined if a branch is predicted taken.

Abstract: An integrated circuit device package. The package includes a package substrate having a conductive bondring disposed thereon. A via is electrically coupled to the bondring. A conductive bondring extension is also disposed on the package substrate. The bondring extension is electrically coupled to the bondring and the via and extends away from the bondring and the via.

Abstract: The present invention is a method and apparatus for updating a timer from a plurality of timing domains. An arbitration circuit arbitrates the update requests from the plurality of timing domains. The plurality of timing domains include at least a counter. The update requests provide the update values. A multiplexer, which is coupled to receive the update values, selects a timer value from the update values. A timer register which is coupled to the multiplexer stores the timer value synchronously with a local clock signal.

Abstract: A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

Abstract: A cryptography unit having a cipher unit and a hash unit coupled in parallel for simultaneous ciphering and hashing. The cipher unit implements a cipher algorithm that operates on a data block having a first predetermined size M. The hash unit implements a hash algorithm on a data block having a second predetermined size N. Buffers of a size Q, where Q is an integer multiple of M and N, are employed to receive the input data into the present invention. A security unit that ensures that the cipher unit and the hash unit operate on the same data block of size Q is also provided.

Abstract: A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop.

Abstract: A pickup chuck having a heat slug for removing heat from a heat generating device that is held within the pickup chuck.

Abstract: A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.

Abstract: Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a particular interrupt input; if it does, determining whether that particular interrupt input is programmed to be a level-triggered interrupt; if it is, determining whether the level-status of that particular interrupt input is active; and, if it is, sending a level-triggered active message for the highest priority pending interrupt, by maintaining the set status of a particular bit.

Abstract: A cooling duct for a computer system with redundant air moving units includes a first inlet that receives a first air flow from a first air moving unit. The cooling duct also includes a second inlet that receives a second air flow from a second air moving unit. A mixing chamber is connected to the first inlet and the second inlet. The mixing chamber receives and mixes the first air flow and the second air flow. A first outlet is connected to the mixing chamber. The first outlet directs the first air flow and the second air flow to a first location. A second outlet is connected to the mixing chamber. The second outlet directs the first air flow and the second air flow to a second location.

Abstract: A method and apparatus to divide a signed integer by a constant power of two using conditionally-executed instructions to choose between a first result in the event that the dividend is a negative signed integer and a second result in the event that the dividend is a positive signed integer, wherein values associated with the first result and the second result are generated simultaneously.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: A data processing device having an apparatus to execute operations out-of-order. The apparatus having an execution unit to execute the set of operations out-of-order. The execution unit, upon executing an operation that generates a first exception, continues to execute operations out-of-order, to avoid deadlock, until an operation of a first type is to be executed. The execution unit flushes a pipeline once the operation of the first type is to be executed.