Abstract: A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floating point instructions. A plurality of tags is associated with the first storage area indicating that locations in the first storage area are either empty or non-empty responsive to the execution of the floating point instructions which modify data contained in the first storage area. Responsive to the receiving of the first instruction which indicates termination of execution of instructions which operate upon the packed data stored in the first storage area, the method sets only the plurality of tags to an empty state. In different embodiments, setting of the plurality of tags to a non-empty state occurs responsive to receiving a second instruction.

Abstract: A method and apparatus for automatically controlling integrated circuit supply voltages includes, according to one embodiment, a primary voltage regulator and a secondary voltage regulator. The primary voltage regulator supplies one of either a first voltage or a second voltage to a first plurality of inputs of an integrated circuit. The secondary voltage regulator conditionally supplies a third voltage to a second plurality of inputs of the integrated circuit in the event the primary voltage regulator supplies the first voltage, with the third voltage being substantially the same as the second voltage.

Abstract: In one embodiment, an anti-aliasing apparatus is disclosed. The anti-aliasing apparatus includes an aperture stop including an array of apertures. Each of the apertures on the aperture stop diffracts light passing therethrough and provides spreading of an image of a point object in a controlled image irradiance distribution. In another embodiment, an optical system is disclosed. The optical system includes a detector array having an array of pixels and an aperture stop positioned between an object plane and the detector array. The aperture stop includes an array of apertures, each of which diffracts light passing therethrough and provides a controlled spreading of the light to cover more than one pixel of the detector array.

Abstract: A circuit that includes at least two driver circuits. Each driver circuit receives analog information and drives a value related to the analog information to an analog bus. Each driver circuit also includes a select transistor to pass the value related to the analog information to the analog bus when the driver circuit is selected. The select transistor includes a source and a bulk. Each driver circuit further includes a bulk potential control circuit (BPCC) to couple the bulk to the source when the driver circuit is selected and to couple the bulk to a voltage supply when the driver circuit is not selected.

Abstract: A voltage regulator includes an output stage, an amplifier and a slew rate control circuit. The output stage furnishes an output voltage, and the amplifier interacts with the output stage to regulate the output voltage. The slew rate control circuit interacts with the output stage to establish a first slew rate for the regulator when the regulator is powering up and a different slew rate for the regulator after the regulator has substantially completed powering up.

Abstract: A device for transferring data between a data processing machine and a smart card is provided. The data processing machine has a drive for receiving a removable storage unit and for reading and writing data from and to said removable storage unit. The device for transferring data between a data processing machine and a smart card includes a housing insertable into the drive. The housing has a recess for receiving a smart card. The device for transferring data further includes a logic circuit, disposed within the housing, for transferring data between the data processing machine and the smart card.

Abstract: The invention provides a method and apparatus for storing complex data in formats which allow efficient complex multiplication operations to be performed and for performing such complex multiplication operations. According to one aspect of the invention, a method for multiplying complex numbers is provided for use in a data processing system. In response to receiving an instruction, eight data elements are read and used to generate a resulting complex number. These eight data elements were previously stored as packed data and include two representations of each of the components of a first and second complex number. Each of these representations is signed such that it represents either the positive or negative of said component. As a result of the manner in which these eight data elements are stored, the resulting complex number represents the product of the first and second complex numbers. According to another aspect of the invention, a machine-readable medium is described.

Abstract: According to one aspect of the invention there is provided a semiconductor chip comprising a semiconductor die, an array of electrical contacts on an integrated circuit in a frontside of the die, and a protective layer on a backside of the die.

Abstract: A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

Abstract: A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactacts.

Abstract: A method and apparatus for reducing the power consumption of an integrated circuit when the core logic of the integrated circuit is in the quiescent or idle state. The method and apparatus includes a phase locked loop (PLL) circuit for generating an internal clock, wherein the frequency of the internal clock is at a predetermined multiple of the frequency of the global clock signal. When the integrated circuit is quiescent, the present invention provides circuitry which permits the internal clock to be slowed to a lower frequency or the internal clock to be frozen to reduce power consumption.

Abstract: A subsystem prevents unauthorized replacement of boot-up firmware (e.g., BIOS) embedded in modifiable non-volatile memory devices such as flash memory. The firmware device is contained in a secure boot device which is responsive to the host processor. The security protection is established by the encryption and decryption of the boot-up instructions using a secret key shared by both the secure boot device and the host processor.

Abstract: A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Abstract: An electronic assembly which has a ring that creates a dam for a thermal grease. The assembly may include an integrated circuit which is mounted to a substrate. The assembly may also include a cover which has an opening that exposes the integrated circuit. The ring is coupled to the integrated circuit and the cover. A thermal element may be placed adjacent to the integrated circuit and the thermal grease. The dam controls the flow of the thermal grease. The opening allows the thermal element to be placed adjacent to the integrated circuit. In one embodiment the thermal element may be attached to the cover by a hinge. The hinge thermal element may compensate for tolerances in the assembly without creating excessive forces on the integrated circuit.

Abstract: A method of forming an interconnect structure using a low dielectric constant material as an intralayer dielectric is described. In one embodiment, the present inventive method comprises the following steps. A conductive structure that is surrounded by a low dielectric constant material on its side surfaces is formed. A first inorganic insulator is formed over at least a portion of the low dielectric constant material. A second inorganic insulator is formed over the first inorganic insulator. A photoresist layer is deposited and then patterned to form an unlanded via in the second inorganic insulator. The second inorganic insulator and a portion of the first inorganic insulator are etched in order to form the unlanded via.

Abstract: A method for locating a critical speed path within a integrated digital circuit. First, the area containing the critical speed path is isolated by selectively enabling a delay of clock driver circuits in the integrated circuit. Isolating the location of the speed path consists of determining a source clock driver that clocks the source of the speed path and a destination clock driver that clocks the destination of the speed path. The possible data path that may be the speed path are then further narrowed down by examining a connection database that lists all the data paths between various circuit areas. Specifically, all the data paths that do not originate at a flip-flop clocked by the source clock driver and end at a flip-flop clocked by the destination clock driver are eliminated. Next, information from a logic simulation trace is examined. The exact time at which the error occurs is identified on the logic simulation trace.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of storing an object within a managed object space of the nonvolatile memory includes the step of determining an object class for the object. Objects of a first class are stored contiguously proceeding from a first end towards a second end of the managed object space to form a first class of space. Objects of a second class are stored contiguously proceeding from the second end towards the first end of managed object space to form a second class of space. A header identifying the object is stored at a bottom of the first class of space. The object is stored at a selected one of the bottom of the first class of space and a bottom of the second class of space in accordance with the object class.

Abstract: A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.

Abstract: During the fabrication of a photolithography mask, double defect-absorbing layers are incorporated to ensure the final mask structure is free of defects. The process begins with a resonant reflector substrate. First and second defect-absorbing layers cover the substrate. The first and second defect-absorbing layers are selected to be repairable if defects form, as well as can be etched selectively relative to each other as well as to the underlying substrate. The first defect-absorbing layer is coated with photoresist. The photoresist is patterned using photolithography. Next, the photoresist pattern is transferred to the first defect-absorbing layer through plasma etching. Any defects arising from the etching step are repaired. Next, the pattern formed in the first defect-absorbing layer is transferred to the second defect-absorbing layer, using the first defect-absorbing layer as a mask. Any defects arising from the etching step are repaired.

Abstract: A novel mask for photolithography in semiconductor processing and fabrication method is disclosed. The mask includes a layer of transmissive material transparent to the wavelength of light to be used deposited thereon. The transmissive material is plasma etched in accordance with a pattern in photoresist deposited thereon to create trench portions in the transmissive material. A layer of absorbing material absorptive to the wavelength of light to be used is deposited within the trench portions. The surface of the mask is then planarized to create a substantially smooth mask layer having trench portions in the transmissive material and absorbing layer portions within the trench portions. If desired, a second layer of transmissive material can be deposited over the smooth mask layer to provide a protective cap to create an overall smooth, flat completed mask surface. The mask is useful for transmissive photolithography applications as well as reflective photolithography applications.