Patents Assigned to Intel Corporation
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Patent number: 11221762Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.Type: GrantFiled: February 13, 2019Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Joydeep Ray, Varghese George, Inder M. Sodhi, Jeffrey R. Wilcox
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Patent number: 11222863Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.Type: GrantFiled: April 1, 2016Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Fay Hua, Christopher M. Pelto, Valluri R. Rao, Mark T. Bohr, Johanna M. Swan
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Publication number: 20220005943Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Jeanette M. Roberts, James S. Clarke, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits
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Publication number: 20220006645Abstract: An apparatus includes a first integrated circuit disposed on a first die, a second integrated circuit disposed on a second die, an interconnect to provide a communication connection between the first die and the second die. The first die comprises a processing circuitry to generate a first message authentication code (MAC) tag using a first message data to be communicated from the first die to the second die and a first cryptographic key, and transmit the first message data and the first MAC tag to the second die via the interconnect.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventor: Santosh Ghosh
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Publication number: 20220005638Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.Type: ApplicationFiled: September 23, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian
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Publication number: 20220004668Abstract: Methods and apparatus relating to a lockable partition in NVMe (Non-Volatile Memory express) drives with drive migration support are described. In an embodiment, a Non-Volatile Memory (NVM) device stores data and partition logic circuitry locks or unlocks a partition on the NVM device in response to a command. The NVM device is physically migratable to a different platform and the NVM device is protected after power loss during runtime. The partition logic circuitry locks or unlocks the partition in response to the command and a cryptographic key. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 16, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Prashant Dewan, Thomas Bowen, Anoop Mukker
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Publication number: 20220004351Abstract: In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Aswin Padmanabhan, Sangeeta Ghangam Manepalli, Kiran K. Velicheti, Robert James Johnston, Chandra Konduru, Todd M. Witter
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Publication number: 20220006630Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Santosh Ghosh, Andrea Basso, Dumitru-Daniel Dinu, Avinash L. Varna, Manoj Sastry
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Publication number: 20220004452Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Wei Yee Koay, Rita H. Wouhaybi, Melissa M. Ortiz, Shahrnaz Azizi, Gayathri Jeganmohan, Lady Nataly Pinilla Pico
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Publication number: 20220004873Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Francesc GUIM BERNAT, Suraj PRABHAKARAN, Kshitij A. DOSHI, Da-Ming CHIANG
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Publication number: 20220006611Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform an incomplete number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format, the plurality of compute nodes comprising at least a first NTT circuit comprising a single butterfly circuit to perform a series of butterfly calculations on input data; and a randomizing circuitry to randomize an order of the series of butterfly calculations.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Santosh Ghosh, Andrea Basso, Dumitru-Daniel Dinu, Avinash L. Varna, Manoj Sastry
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Publication number: 20220004488Abstract: The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to access the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) coupled to the one or more registers based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Barun Bikash Paul, Rita Deepak Gupta, Suresh Thirumandas
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Publication number: 20220004627Abstract: An apparatus and method include generating a trusted computing base (TCB) component identifier (TCI) of a current component of a computing system, generating a compound device identifier (ID) (CDI) of the current component from a CDI of a previous component of the computing system and the TCI of the current component, and determining a size of the TCI of the current component. The system and method further include summing the size of the TCI of the current component and the cumulative size of the TCIs of previous components of the computing system to generate a current cumulative size, combining the current cumulative size and the CDI of the current component, and including the combined current cumulative size and the CDI of the current component in a chain of measurements for attestation of the computing system.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Ned M. Smith, Daniel Middleton
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Publication number: 20220004342Abstract: An embodiment of an electronic apparatus may include a substrate and a controller coupled to the substrate, the controller including circuitry to control access to a NAND-based storage media that includes a plurality of NAND devices located on the substrate and organized into two or more physical clusters with each NAND device uniquely assigned to one of the two or more physical clusters, perform data access to a first physical cluster of the two or more physical clusters at a first bandwidth, and perform data access to a second physical cluster of the two or more physical clusters at a second bandwidth that is slower than the first bandwidth. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Jorge Ulises Martinez Araiza, Michael Leslie Roy, Andrew Morning-Smith
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Publication number: 20220005286Abstract: This disclosure describes methods, apparatus, and systems related to media access control (MAC) range extension. A device may cause to append a training field to each of one or more beacon frames. The device may cause to send the one or more beacon frames directionally using a sector sweep to one or more responder devices during a first interval. The device may determine an extended schedule element to be sent to the one or more responder devices, the extended schedule element including one or more directional antenna sectors to be used by the device during a second interval. The device may identify a first frame from a first responder device, during the second interval, wherein the first frame is received on a directional antenna sector of the one or more directional antenna sectors corresponding to an operating sector of the first responder device.Type: ApplicationFiled: June 30, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Cheng Chen, Carlos Cordeiro, Claudio Da Silva, Solomon Trainin, Alexander Maltsev, Artyom Lomayev
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Publication number: 20220006682Abstract: A data transmission system includes a transmitter circuit. The transmitter circuit receives regular data bits and auxiliary data bits. The transmitter circuit encodes a first subset of the regular data bits to generate a first subset of encoded data comprising pairs of symbols that are used in quadrature amplitude modulation. The transmitter circuit encodes the auxiliary data bits and a second subset of the regular data bits to generate a second subset of the encoded data comprising at least one pair of symbols that are unused for encoding by the quadrature amplitude modulation. The transmitter circuit generates a modulated output signal that indicates the first and second subsets of the encoded data using pulse amplitude modulation.Type: ApplicationFiled: September 19, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventor: David Mendel
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Publication number: 20220006884Abstract: Techniques for reassembling fragmented datagrams are disclosed. Packets may be received and classified. Packets of a fragmented datagram may be stored for later reassembly. In the illustrative embodiment, a datagram is reassembled based on an identified class of service associated with the datagram. Additionally or alternatively, in the illustrative embodiment, a replay window of a replay attack detector may be tuned based on hardware performance of a compute device.Type: ApplicationFiled: September 16, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: John J. Browne, Chris M. MacNamara, Declan W. Doherty, Konstantin Ananyev
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Publication number: 20220004468Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Rita Gupta, Mark Schmisseur, Dimitrios Ziakas
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Publication number: 20220004398Abstract: An apparatus is disclosed.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Gregory Iovino, Bharat Pillilli, Neel Piyush Shah, Philip Rogers, David Palmer
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Publication number: 20220006568Abstract: This disclosure describes systems, methods, and devices related to an enhanced retry count for an uplink (UL) multi-user (MU) transmission. A device may identify a trigger frame received from a first device on a wireless communication channel. The device may determine a quality of service counter associated with an access category. The device may cause to send a frame to the first device based at least in part on the trigger frame. The device may determine an error condition associated with the frame. The device may refrain from incrementing the quality of service counter based on the error condition.Type: ApplicationFiled: June 23, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Po-Kai Huang, Laurent Cariou
