Patents Assigned to Intel Corporation
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Patent number: 11025411Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set.Type: GrantFiled: March 6, 2018Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Francesc Guim Bernat, Suraj Prabhakaran, Kshitij Doshi, Timothy Verrall
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Patent number: 11023244Abstract: In one embodiment, a link training controller is to train a link. The link training controller may be configured to: update a first link parameter of a link setting for the link to a first value; write data to the memory; read the data from the memory using the first value of the first link parameter; and in response to a determination that the data read from the memory does not match the data written to the memory, send an in-band link recovery command to the memory via the link to cause the memory to participate in a link recovery protocol with the apparatus. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2017Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Ee Loon Teoh, Eng Hun Ooi, Roger K. Cheng
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Patent number: 11026351Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a closed cooling loop thermally coupled to one or more processors disposed on a circuit board of the computing apparatus. The closed cooling loop circulates a dielectric fluid to absorb heat from the processor. A portion of the dielectric fluid is evaporated from the processor heat absorbed by the dielectric fluid. A heat exchanger is coupled to the circuit board and thermally coupled to the closed cooling loop. The heat exchanger is to include a coolant flow to remove heat from the dielectric fluid circulated through the portion of the closed cooling loop thermally coupled to the heat exchanger. A vapor portion of the dielectric fluid is condensed from the heat removed by the coolant flow. Other embodiments may be described and/or claimed.Type: GrantFiled: September 25, 2015Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Devdatta P. Kulkarni, Richard J. Dischler
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Patent number: 11023824Abstract: Methods, apparatus, and machine-readable mediums are described for selecting a training set from a larger data set. Samples are divided into a training set and a validation set. Each set meets one or more conditions. For each class to be modeled, multiple training sets are created. Models are trained on each of the multiple training sets. A size of samples for each class is determined based upon the trained models. A training data set that includes a number of samples based upon the determined size of samples is created.Type: GrantFiled: August 30, 2017Date of Patent: June 1, 2021Assignee: Intel CorporationInventor: Luis Sergio Kida
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Patent number: 11019864Abstract: A smart fabric may include a smart material such as an Electroactive Polymer (EAP). An adaptive garment formed from the smart fabric may change textile density based on user needs, sensor states, context, and other inputs. In various embodiments, the EAP enables the adaptive garment to change textile density based on a sport or activity, based on calendar or scheduled events, or based on user preferences. In various embodiments, these smart fabrics may be implemented in sporting garments, uniforms, multiple-day clothing (e.g., for travel or military usage), furniture fabric, curtains, or other implementations.Type: GrantFiled: June 14, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Tomer Rider, Shahar Taite
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Patent number: 11025627Abstract: Various systems and methods of scalable and secure resource isolation and sharing for Internet of Things (IoT) networks, are described. Techniques for requesting inter-domain resource access and enabling resource sharing with use of an inter domain token are also described. In an example, communications in an IoT network to establish connectivity between a first device in a first domain and a second device in a second domain may include: receiving, from the first device at a collaboration cloud service, a request to access a resource of the second device; requesting and receiving, from an authorization provider, an inter-domain authorization token; and requesting, from the second device, access to the resource using the inter-domain authorization token; communications from the first device to access the second device are then performed between the first device and the second device based on a session key obtained with the inter-domain authorization token.Type: GrantFiled: January 9, 2018Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Weigang Li, Ned M. Smith, Changzheng Wei
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Patent number: 11024041Abstract: A mechanism is described for facilitating depth and motion estimation in machine learning environments, according to one embodiment. A method of embodiments, as described herein, includes receiving a frame associated with a scene captured by one or more cameras of a computing device; processing the frame using a deep recurrent neural network architecture, wherein processing includes simultaneously predicating values associated with multiple loss functions corresponding to the frame; and estimating depth and motion based the predicted values.Type: GrantFiled: December 10, 2018Date of Patent: June 1, 2021Assignee: INTEL CORPORATIONInventors: Koba Natroshvili, Kay-Ulrich Scholl
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Patent number: 11023326Abstract: An embodiment of a semiconductor apparatus for use with a persistent storage media may include technology to detect a power interruption event, and track an amount of off-time for a persistent storage media after the detected power interruption event. Other embodiments are disclosed and claimed.Type: GrantFiled: March 6, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Andrew Morning-Smith, Brian Mcfarlane, Emily P. Chung, William Glennan
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Patent number: 11023385Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.Type: GrantFiled: May 26, 2020Date of Patent: June 1, 2021Assignee: INTEL CORPORATIONInventors: Kiran S. Panesar, Michael A. Goldsmith
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Patent number: 11024601Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.Type: GrantFiled: December 21, 2017Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
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Patent number: 11023622Abstract: A method performed by a processor of an aspect includes accessing an encrypted copy of a protected container page stored in a regular memory. A determination is made whether the protected container page was live stored out, while able to remain useable in, protected container memory. The method also includes either performing a given security check, before determining to store the protected container page to a destination page in a first protected container memory, if it was determined that the protected container page was live stored out, or not performing the given security check, if it was determined that the protected container page was not live stored out. Other methods, as well as processors, computer systems, and machine-readable medium providing instructions are also disclosed.Type: GrantFiled: June 29, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Carlos V. Rozas, Mona Vij, Somnath Chakrabarti
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Patent number: 11023258Abstract: Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations.Type: GrantFiled: December 30, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Neeraj S. Upasani, Jeanne Guillory, Wojciech Powiertowski, Sergiu D Ghetie, Mohan J. Kumar, Murugasamy K. Nachimuthu
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Patent number: 11022792Abstract: Aspects of the embodiments are directed to coupling a permanent magnet (PM) with a microelectromechanical systems (MEMS) device. In embodiments, an adhesive, such as an epoxy or resin or other adhesive material, can be used to move the PM towards the MEMS device to magnetically couple the PM to the MEMS device. In embodiments, an adhesive that is configured to shrink up on curing can be applied (e.g., using a pick and place tool) to a location between the MEMS device and the PM. As a result of curing, the adhesive can pull the PM towards the MEMS device. In embodiments, an adhesive that is configured to expand as a result of curing can be applied to a location between the PM and a sidewall of the chassis. As a result of curing, the adhesive can push the PM towards the MEMS device. The adhesive can also secure the PM in place.Type: GrantFiled: December 27, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Kyle Yazzie, Anna M. Prakash, Suriyakala Ramalingam, Liwei Wang, Robert Starkston, Arnab Choudhury, Sandeep S. Iyer, Amanuel M. Abebaw, Nick Labanok
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Patent number: 11024538Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.Type: GrantFiled: December 31, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Kevin L. Lin, Tayseer Mahdi, Jessica M. Torres, Jeffery D. Bielefeld, Marie Krysak, James M. Blackwell
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Patent number: 11023067Abstract: A device may be controlled using a fingerprint input. Data indicative of a fingerprint is received from a sensor. It is determined that the fingerprint is associated with a first finger profile that is usable to distinguish a first finger from other fingers of a user of the device. A user control that is associated with the finger profile is identified. The user control is configured to control a setting of a function executing on the device. The user control is input to control the first setting.Type: GrantFiled: December 19, 2018Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Tim Schoenauer, Bernhard Raaf
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Patent number: 11024559Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.Type: GrantFiled: April 1, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Joshua Heppner, Mitul Modi
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Patent number: 11024356Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.Type: GrantFiled: September 9, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
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Patent number: 11024180Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to validate data communicated by a vehicle. An example apparatus an anomaly detector to, in response to data communicated by a vehicle, at least one of compare an estimated speed with a reported speed or compare a location of the vehicle with a reported location. The apparatus including the anomaly detector further to generate an indication of the vehicle in response to the comparison. The apparatus further includes a notifier to discard data sent by the vehicle and notify surrounding vehicles of the data communicated by the vehicle.Type: GrantFiled: December 27, 2018Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Liuyang Yang, Yair Yona, Moreno Ambrosin, Xiruo Liu, Hosein Nikopour, Shilpa Talwar, Kathiravetpillai Sivanesan, Sridhar Sharma, Debabani Choudhury, Kuilin Clark Chen, Jeffrey Ota, Justin Gottschlich
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Patent number: 11023233Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.Type: GrantFiled: February 9, 2016Date of Patent: June 1, 2021Assignee: INTEL CORPORATIONInventors: Michael Mishaeli, Jason W. Brandt, Gilbert Neiger, Asit K. Mallick, Rajesh M. Sankaran, Raghunandan Makaram, Benjamin C. Chaffin, James B. Crossland, H. Peter Anvin
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Patent number: 11025214Abstract: Described is high-current drive class AB operational trans-conductance amplifier (OTA) output that can operate under low supply voltages (e.g., below 0.9 V) while maintaining desired functionality (e.g., reliable startup behavior, well-defined biasing currents, phase margins for improved stability) over a broad range of process, voltage, and temperature variations. The class AB OTA comprises a pre-amplifier stage, and a differential OTA output stage coupled to the pre-amplifier stage, wherein the differential OTA output stage comprises at least four folded cascode transistors.Type: GrantFiled: January 28, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventor: Krzysztof Dufrene