Patents Assigned to Intel Corporation
  • Patent number: 10580143
    Abstract: Techniques for high-fidelity three-dimensional (3D) reconstruction of a dynamic scene as a set of voxels are provided. One technique includes: receiving, by a processor, image data from each of two or more spatially-separated sensors observing the scene from a corresponding two or more vantage points; generating, by the processor, the set of voxels from the image data on a frame-by-frame basis; reconstructing, by the processor, surfaces from the set of voxels to generate low-fidelity mesh data; identifying, by the processor, performers in the scene from the image data; obtaining, by the processor, high-fidelity mesh data corresponding to the identified performers; and merging, by the processor, the low-fidelity mesh data with the high-fidelity mesh data to generate high-fidelity 3D output. The identifying of the performers includes: segmenting, by the processor, the image data into objects; and classifying, by the processor, those of the objects representing the performers.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: March 3, 2020
    Assignee: INTEL Corporation
    Inventors: Sridhar Uyyala, Ignacio J. Alvarez, Bradley A. Jackson, Deepak S. Vembar
  • Patent number: 10579382
    Abstract: An apparatus and method for scalable interrupt reporting.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Rajesh Sankaran, Ankur Shah, Bryan White, Hema Nalluri, David Puffer, Murali Ramadoss, Altug Koker, Aditya Navale, Balaji Vembu
  • Patent number: 10580200
    Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Brent E. Insko, Prasoonkumar Surti
  • Patent number: 10581444
    Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Young Min Park, Mark Elzinga
  • Patent number: 10580105
    Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Kun Tian, Yao Zu Dong, Zhiyuan Lv
  • Patent number: 10580973
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 3, 2020
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
  • Patent number: 10580108
    Abstract: An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian, Tian Zhang, Yulei Zhang
  • Patent number: 10580756
    Abstract: Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond bondpads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventor: Hungying L. Lo
  • Patent number: 10578880
    Abstract: With a device comprising a directional antenna, obtain an interaction profile for an augmentable object and augment a sensory experience of the augmentable object according to the interaction profile.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Tomer Rider, Ron Ferens, Amit Moran
  • Patent number: 10579530
    Abstract: In an embodiment, a processor includes a plurality of cores, with at least one core including prefetch logic. The prefetch logic comprises circuitry to: receive a prefetch request; compare the received prefetch request to a plurality of entries of a prefetch filter cache; and in response to a determination that the received prefetch request matches one of the plurality of entries of the prefetch filter cache, drop the received prefetch request. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Stanislav Shwartsman, Ron Rais
  • Patent number: 10576590
    Abstract: Embodiments herein relate to torque controlled drivers to simultaneously drive fasteners to secure a thermal transfer device to an integrated circuit package. In various embodiments, a torque controlled driver may include a gearbox, a driver with a torque controller and a motor with a rotating shank, a motor gear coupled concentrically with the rotating shank, a bit drive gear in rotational engagement with the motor gear to drive a bit sized to drive a fastener to secure a thermal transfer device to an integrated circuit package, where the gearbox is to hold the motor gear in a position about a motor gear rotational axis and the drive gear about a drive gear rotational axis such that the motor gear and the bit drive gear maintain rotational engagement as the motor gear rotates. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Batsegaw K. Gebrehiwot, Joseph B. Petrini, Nicholas S. Haehn, Shankar Devasenathipathy, Robert L. Sankman, Alfredo G. Cardona
  • Publication number: 20200067816
    Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Tejpal Singh, Shawna M. Liff, Gerald S. Pasdast, Johanna M. Swan
  • Publication number: 20200068167
    Abstract: Techniques for video analytics of captured video content are described. An apparatus may comprise a flash memory, a serial bus, and a processor circuit coupled to the flash memory and the serial bus. The processor circuit may comprise a multi-core central processing unit (CPU) and an integrated graphics processing unit (GPU). The processor circuit may receive captured video content via a local communication link, perform video analytics on the captured video content; and send data associated with the performed video analytics to a network interface, for communication to a remote device via a network communication link. Other examples are described and claimed.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Yen Hsiang Chew, Boon Hee Thomas Kam, Esther Chee Hsiang Cheng, Ivan Yu Kit Ho
  • Publication number: 20200067526
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: September 6, 2019
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Md. Mohiuddin Mazumder, Subas Bastola, Kai Xiao
  • Publication number: 20200066830
    Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Krishna Bharath, Wei-Lun Jen, Huong Do, Amruthavalli Alur
  • Publication number: 20200066634
    Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
  • Publication number: 20200066659
    Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Omkar Karhade, Martin Rodriguez, Gregorio R. Murtagian
  • Publication number: 20200064523
    Abstract: The present disclosure is directed to systems and methods useful for providing a metasurface lens formed by a plurality of multi-piece optical structures disposed on, about, or across at least a portion of the surface of substrate member. Each of the plurality of multi-piece optical structures includes a solid cylindrical core structure surrounded by a hollow cylindrical core structure such that a gap having a defined width forms between the solid cylindrical core structure and the hollow cylindrical structure surrounding the solid core. The width of the gap determines the optical performance of the metasurface lens. The multi-component optical structures forming the metasurface lens advantageously produce little or no phase shift in the electromagnetic energy passing through the metasurface lens, thereby beneficially providing an optical device having minimal or no dispersion and/or chromatic aberration.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Prashant Majhi, Kunjal Parikh, Paul West
  • Publication number: 20200067694
    Abstract: Techniques for securely provisioning a set of enclaves are described. A contract owner may register with a shared registry. A subset of enclaves may be selected to be provisioned from among a plurality of enclaves. A keyshare may be requested from one or more provisioning services for each of the subset of enclaves to be provisioned. The requested keyshares may be received from each provisioning service for each of the subset of enclaves to be provisioned. For each of the selected enclaves, the received keyshares may be sent for verification by the enclave. Each of the selected enclaves may send an authenticated and encrypted key derived from the received keyshares.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Applicant: INTEL CORPORATION
    Inventors: Mic Bowman, Andrea Miele
  • Publication number: 20200066626
    Abstract: Disclosed herein are pocket structures, materials, and methods for integrated circuit (IC) package supports. For example, in some embodiments, an IC package support may include: an interconnect pocket having sidewalls provided by a dielectric material; and a conductive contact at a bottom of the interconnect pocket, wherein the conductive contact includes a first metal material and a second metal material, the first metal material provides a bottom surface of the interconnect pocket and is in contact with the dielectric material, the second metal material has a different composition than the first metal material, and the second metal material is in contact with the dielectric material.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Jason M. Gamba, David Unruh, Adrian Kemal Bayraktaroglu, Thomas S. Heaton