Abstract: Methods for improving end-to-end congestion reaction using adaptive routing and congestion-hint based throttling for IP-routed datacenter networks and associated apparatus. In connection with forwarding packets between sending and receiving endpoints coupled to one or more networks, one or more network switches are configured to detect current or approaching congestion conditions, generate congestion notification packets (CNPs), and return the CNPs to sending endpoints. The CNPs may be routed using one or more adaptive routing mechanisms to forward the CNPs along non-congested paths or may be forwarded along a fastest path to a sender. The CNPs further may comprise meta-data including a flow identifier associated with a packet sent from an endpoint, a congestion level for the flow, and a timestamp.

Abstract: Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand.

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Abstract: Examples described herein relate to a network agent, when operational, to: receive a packet, determine transmit rate-related information for a sender network device based at least on operational and telemetry information accumulated in the received packet, and transmit the transmit rate-related information to the sender network device. In some examples, the network agent includes a network device coupled to a server, a server, or a network device. In some examples, the operational and telemetry information comprises: telemetry information generated by at least one network device in a path from the sender network device to the network agent.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Abstract: Methods, apparatus, systems and articles of manufacture for continuous monitoring of telemetry in the field are disclosed. An example apparatus includes a fault predictor to predict an outcome of one or more execution paths. A resolution handler is to determine one or more resolution strategies for an execution path and apply a resolution strategy. An impact trainer is to determine whether the predicted outcome of the execution path has changed and store impact data of one or more applied resolution strategies.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.

Abstract: A data processing system comprises a processing core to execute a basic input/output system (BIOS) as part of a boot process. The data processing system also comprises static random-access memory (SRAM) in communication with the processing core. The data processing system also comprises a pre-BIOS component in communication with the SRAM. The pre-BIOS component is configured to execute a pre-BIOS block before the processing core begins executing the BIOS. The pre-BIOS block, when executed by the pre-BIOS component, causes the pre-BIOS component to (a) initialize the pre-BIOS component, (b) measure an amount of time taken to initialize the pre-BIOS component, and (c) save the measured amount of time to the SRAM as a pre-BIOS boot-time record. Other embodiments are described and claimed.

Abstract: A communication device including one or more processors configured to determine a first signal component of a received modulated signal; determine a second signal component of the received modulated signal; generate a phase shift of the first signal component; generate a phase shift of the second signal component; compare the phase shift of the first signal component and the phase shift of the second signal component with each other; and generate a plurality of constellation points, wherein each of the plurality of constellation point is based on the determination of the first signal component, the determination of the second signal component, and the comparison.

Abstract: Systems, apparatuses and methods may provide for technology that initializes an integrated memory of a processor during a boot sequence and conducts a runtime initialization of an external system memory associated with the processor. The technology may also bypass the runtime initialization of the external system memory during the boot sequence.

Abstract: Display pixels having integrated memory are disclosed. A disclosed example memory pixel includes a light emitter on a semiconductor substrate, memory co-located with the light emitter on the same semiconductor substrate, and a comparator in circuit with the memory, the comparator to control a flow of electrical current to the light emitter based on pixel data from the memory and timing information.

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.

Abstract: This disclosure describes systems, methods, and devices related to enhanced sounding for secure mode wireless communications. A device may generate a channel sounding symbol comprising a first subcarrier and a second subcarrier, wherein a first amplitude of the first subcarrier is different than a second amplitude of the second subcarrier. The device may generate a channel sounding signal comprising the channel sounding symbol. The device may send the channel sounding signal to a second device.

Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element.

Abstract: An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Abstract: Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

Abstract: An electronic computing device with a self-shielding antenna. An electronic computing device may include a frame, an antenna, and an antenna shielding. The frame includes a top cover and a bottom cover. Electronic components are included in a space formed between the top cover and the bottom cover. The antenna is for wireless transmission and reception and included in the frame near an edge of the frame. The antenna shielding is disposed around the antenna for providing electro-magnetic shielding from radio frequency (RE) noises generated from the electronic components included in the frame. The antenna shielding may be a metal wall disposed between the top cover and the bottom cover around the antenna. The frame may be a metallic frame and may include a cut-out in the top cover and the bottom cover above and below the antenna, and a non-metallic cover may be provided in the cut-out.

Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.