Abstract: Techniques related to feature detection and matching fisheye images are discussed. Such techniques include determining a geometric constraint for the feature matching using match results from a first image based feature matching and generating resultant matches based on applying the geometric constraint and a second image based feature matching that applies a looser image based feature matching requirement than the image based feature matching.

Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.

Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract: An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

Abstract: Embodiments are generally directed to minimum or maximum sample indexing in a control surface. An embodiment of an apparatus includes a graphics processor including: a sampler to sample a value; one or more of a color unit or a depth unit; and at least one minimum or maximum sample (min/max) setter subunit for the color unit or depth unit, the min/max setter subunit to receive a new sample value, store the sample value in a resource containing a plurality of sample values, and update indexing include index values for one or more of a minimum sample value and a maximum sample value in the plurality of sample values of the resource.

Abstract: An apparatus of a Fifth Generation NodeB (gNB) to operate in a License Assisted Access (LAA) system configures a transmission initiation time interval contention window size (CWS) of N number of subframes between Category 4 Listen Before Talk (LBT) uplink (UL) transmissions by a user equipment (UE) operating in the LAA system, and a memory to store a value of N which can have a value 6 or greater or 10 or greater. An apparatus of a UE to operate in an LAA system decodes a configuration from the gNB of a transmission initiation time interval contention CWS of N number of subframes between Category 4 LBT UL transmissions in the LAA system. The CWS is increased to a next higher value when an UL grant or an autonomous UL (AUL) downlink feedback indicator (DFI) is not received before the expiration of a timer.

Abstract: There is disclosed in one example a fiberoptic communication circuit for wavelength division multiplexing (WDM) communication, including: an incoming waveguide to receive an incoming WDM laser pulse; an intermediate slab including a demultiplexer circuit to isolate n discrete modes from the incoming WDM laser pulse; n outgoing waveguides to receive the n discrete modes, the outgoing waveguides including fully-etched rib-to-channel waveguides; and an array of n photodetectors to detect the n discrete modes.

Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

Abstract: A circuit system includes an integrated circuit package, first and second memory modules, and a base circuit board. The integrated circuit package houses a main integrated circuit die. The first memory module has a first circuit board and first memory integrated circuit dies coupled to the first circuit board. The second memory module has a second circuit board and second memory integrated circuit dies coupled to the second circuit board. The base circuit board is coupled to the integrated circuit package and to the first and second memory modules. The base circuit board includes conductors that couple the integrated circuit package to the first and second memory modules. The second memory module has a reverse orientation on the base circuit board relative to the first memory module such that the second memory integrated circuit dies face away from the first memory integrated circuit dies.

Abstract: An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.

Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.

Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

Abstract: Embodiments of mechanisms for dynamic media content type streaming management for mobile devices are generally described herein. In some embodiments, the mobile device may receive selection input pertaining to generating output from a media file containing at least two of audio data, video data, and closed-captioning data, the selection input selecting at least one of audio, video, and closed-captioning to be output during play of the media content. In some embodiments, the mobile device may generate an audio output as a signal in response to the selection input including audio. In some embodiments, the mobile device may generate a video output as a signal in response to the selection input including video. In some embodiments, the mobile device may generate a closed-captioning output as a signal in response to selection input including closed-captioning.

Abstract: Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such semiconductor devices.