Abstract: A multilayer package and wireless communication device for high frequency communications, for example large-scale millimeter (mmWave) phased arrays having wide scanning range, wide bandwidth, and high efficiency. The multilayer package comprises a plurality of patch antennas disposed on a first substrate, a plurality of slotted patch antennas disposed on a third substrate, the first substrate and the third substrate being disposed on opposing sides of a second substrate, a plurality of antenna feeds disposed on a fourth substrate, the fourth substrate being disposed adjacent to the third substrate, a plurality of dipoles disposed on the first substrate, the second substrate, the third substrate, and the fourth substrate, and an impedance transformer, disposed within one or more additional substrates. The wireless communication device can include the multilayer package and an integrated circuit, wherein each of the plurality of antenna feeds is coupled to the integrated circuit by the impedance transformer.

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

Abstract: An optical spectral analyzer for measuring an optical multi-channel signal by separating the multi-channel signal and measuring a plurality of single-channel signals simultaneously. The spectral analyzer can include a demultiplexer configured to receive the multi-channel signal. The multi-channel signal can be a multi-channel wavelength range. The demultiplexer can separate the multi-channel signal into the plurality of single-channel signals including a first single-channel signal and a second single-channel signal. The spectral analyzer can include a plurality of optical paths. The plurality of optical paths can include a plurality of respective detectors for measuring an optical power of the respective single-channel signals. The detectors can convert the optical power of the respective single-channel signals to corresponding electrical signals.

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices.

Abstract: Embodiments provide for a graphics processing apparatus including logic to receive data from an input buffer. The data can define a set of data points, where each data point includes one or more dimensions. The logic is configured to process the received data points to perform in-place construct a left-balanced and complete point k-d tree of the data points within the input buffer.

Abstract: A protocol handler communicatively coupled to client devices in an internet of things (IoT) network can operate to update manufacturer specific parameters for corresponding different protocols. A protocol component of the protocol handler can map updates from different manufacturers or different manufacturer servers to a translator dataset of a look-up table. The updates can be mapped to an IoT protocol as IoT parameters based on the associations of the look-up table between the different protocols. An IoT translator component can translate communications back and forth from manufacturers or their servers of different communications protocols to one or more of the client devices and vice versa, in which the client devices are associated with different protocols, and can also communicate to one another via the IoT translator in the IoT protocol.

Abstract: Systems, apparatuses and methods of creating virtual objects may provide for segmenting one or more objects in a scene and highlighting a selected object from the segmented one or more objects based on an input from a user. In one example, a scene-based virtual object is created from the selected object and a behavior is assigned to the scene-based virtual object.

Abstract: Systems and methods for dynamically creating collaborative teams and managing collaborative work of a team are generally disclosed herein. One example embodiment includes the dynamic creation of a collaborative team by creating an association between team members via a managing module. The managing module may be capable of managing, among other things, team members on a team, tasks and goals of each member of the team, as well as documentation associated with the team. In some embodiments, the managing module may use a chat or messaging protocol to manage collaborative modifications to documents of the team.

Abstract: Technologies for secure enumeration of USB devices include a computing device having a USB controller and a trusted execution environment (TEE). The TEE may be a secure enclave protected secure enclave support of the processor. In response to a USB device connecting to the USB controller, the TEE sends a secure command to the USB controller to protect a device descriptor for the USB device. The secure command may be sent over a secure channel to a static USB device. A driver sends a get device descriptor request to the USB device, and the USB device responds with the device descriptor. The USB controller redirects the device descriptor to a secure memory buffer, which may be located in a trusted I/O processor reserved memory region. The TEE retrieves and validates the device descriptor. If validated, the TEE may enable the USB device for use. Other embodiments are described and claimed.

Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

Abstract: An apparatus and method are described for using a touch screen device to control an external display. For example, one embodiment of an apparatus comprises a touch screen to receive user touch input and display images; a processor communicatively coupled to the touch screen; a wireless session management module to establish and maintain a wireless display connection with an extended screen responsive to commands from the processor; and the processor to execute a process responsive to the user touch input to transform the touch screen or a portion thereof to a remote control touchpad device usable to provide control functions for content displayed on the extended screen.

Abstract: Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.

Abstract: Techniques are provided for perception enhancement of light fields (LFs) for use in integral display applications. A methodology implementing the techniques according to an embodiment includes receiving one or more LF views and a disparity map associated with each LF view. The method also includes quantizing the disparity map into planes, where each plane is associated with a selected range of depth values. The method further includes slicing the LF view into layers, where each layer comprises pixels of the LF view associated with one of the planes. The method further includes shifting each of the layers in a lateral direction by an offset distance. The offset distance is based on a viewing angle associated with the LF view and further based on the depth values of the associated plane. The method also includes merging the shifted layers to generate a synthesized LF view with increased parallax.

Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: Methods and systems may provide for receiving a physiological signal from a sensor configuration associated with a mobile device. A qualitative analysis may be conducted for each of a plurality of noise sources in the physiological signal to obtain a corresponding plurality of qualitative ratings. In addition, at least the plurality of qualitative ratings may be used to determine whether to report the physiological signal to a remote location. In one example, a quantitative analysis is conducted for each of the plurality of noise sources to obtain an overall quality level, wherein the overall quality level is also used to determine whether to report the physiological signal to the remote location.

Abstract: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.

Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.