Patents Assigned to Intel Corporations
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Patent number: 12223427Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: May 30, 2023Date of Patent: February 11, 2025Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
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Patent number: 12223417Abstract: A mechanism is described for facilitating smart convolution in machine learning environments. An apparatus of embodiments, as described herein, includes one or more processors including one or more graphics processors, and detection and selection logic to detect and select input images having a plurality of geometric shapes associated with an object for which a neural network is to be trained. The apparatus further includes filter generation and storage logic (“filter logic”) to generate weights providing filters based on the plurality of geometric shapes, where the filter logic is further to sort the filters in filter groups based on common geometric shapes of the plurality of geographic shapes, and where the filter logic is further to store the filter groups in bins based on the common geometric shapes, wherein each bin corresponds to a geometric shape.Type: GrantFiled: May 24, 2023Date of Patent: February 11, 2025Assignee: INTEL CORPORATIONInventor: Dhawal Srivastava
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Patent number: 12224015Abstract: Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.Type: GrantFiled: April 21, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Ali Khakifirooz, Rezaul Haque, Dhanashree Kulkarni, Bayan Nasri
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Patent number: 12223585Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.Type: GrantFiled: October 3, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Karol Szerszen, Prasoonkumar Surti, Gabor Liktor, Karthik Vaidyanathan, Sven Woop
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Patent number: 12224202Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.Type: GrantFiled: July 21, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron Lilak, Ehren Mannebach, Patrick Morrow, Anh Phan, Willy Rachmady, Hui Jae Yoo
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Patent number: 12223035Abstract: A method comprises generating, during a software build process conducted in a trusted build environment, a trusted log comprising a plurality of records of actions performed during the software build process and a plurality of identifiers of tools used to perform the actions, aggregating the plurality of records of actions and the plurality of identifiers into a build certificate file, generating a digital signature to be applied to the build certificate, and publishing the build certificate in association with one or more build artifacts generated by the software build process.Type: GrantFiled: December 15, 2021Date of Patent: February 11, 2025Assignee: INTEL CORPORATIONInventors: Piotr Zmijewski, Arkadiusz Berent, Mateusz Bronk
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Patent number: 12220822Abstract: Apparatus, systems, articles of manufacture, and methods for robot movement are disclosed. An example robot movement apparatus includes a sequence generator to generate a sequence of context variable vectors and policy variable vectors. The context variable vectors are related to a movement target, and the policy variable vectors are related to a movement trajectory. The example apparatus includes a calculator to calculate an upper policy and a loss function based on the sequence. The upper policy is indicative of a robot movement, and the loss function is indicative of a degree to which a movement target is met. The example apparatus also includes a comparator to determine if the loss function satisfies a threshold and an actuator to cause the robot to perform the robot movement of the upper policy when the loss function satisfies the threshold.Type: GrantFiled: October 23, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Zhongxuan Liu, Zhe Weng
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Patent number: 12223353Abstract: Apparatuses to synchronize lanes that diverge or threads that drift are disclosed. In one embodiment, a graphics multiprocessor includes a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types. A regroup engine (or regroup circuitry) regroups threads into a third group having threads of the first instruction type and a fourth group having threads of the second instruction type.Type: GrantFiled: October 5, 2023Date of Patent: February 11, 2025Assignee: INTEL CORPORATIONInventors: Valentin Andrei, Subramaniam Maiyuran, SungYe Kim, Varghese George, Altug Koker, Aravindh Anantaraman
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Patent number: 12224326Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.Type: GrantFiled: October 10, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Rishabh Mehandru, Pratik A. Patel, Ralph T. Troeger, Szuya S. Liao
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Patent number: 12222881Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.Type: GrantFiled: April 15, 2021Date of Patent: February 11, 2025Assignee: INTEL CORPORATIONInventors: Swadesh Choudhary, Mahesh Wagh, Debendra Das Sharma
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Patent number: 12222873Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed.Type: GrantFiled: September 13, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Rupin Vakharwala, Vedvyas Shanbhogue
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Patent number: 12224940Abstract: Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.Type: GrantFiled: October 29, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Malek Musleh, Gene Wu, Anupama Kurpad, Allister Alemania, Roberto Penaranda Cebrian, Robert Southworth, Pedro Yebenes Segura, Curt E. Bruns, Sujoy Sen
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Patent number: 12222790Abstract: A power management scheme for USB systems. For Mobile systems that has re-timer, a handshake is used between power delivery (PD) controller, re-timer and embedded controller (EC) so that the PD controller can end higher wattage power contract on USB-C connector after TBT/USB4 link is in low power (CLd/U3) and during system low power transition allowing Dynamic Platform and Thermal Framework (DPTF) framework to boost CPU performance and enhance battery capacity respectively. The same solution can be extended to desktop segment to allow PD controller to lower the USB-C power contract with connected devices before switching to standby rail. For mobile systems that are without re-timer, a handshake is used between BIOS, PD controller and EC so that PD controller can end higher wattage power contract on USB-C connector after TBT/USB4 link is in low power (CLd/U3) and during system low power transition.Type: GrantFiled: December 22, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Venkataramani Gopalakrishnan, Ravishankar S., Yaniv Hayat, Yi Jen Huang
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Patent number: 12223358Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.Type: GrantFiled: June 17, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Anil Rao, Debendra Das Sharma
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Patent number: 12223371Abstract: Systems and methods for inter-kernel communication using one or more semiconductor devices. The semi-conductor devices include a kernel. The kernel may be in an inactive state unless performing an operation. One kernel of a first device may monitor data for an event. Once an event has occurred, the kernel sends an indication to a first inter-kernel communication circuitry. The inter-kernel communication circuitry determines an activation function of a plurality of activation functions is to be generated, generates the activation function, and transmits the activation function to a second kernel of a second device to waken and perform a function using a peer-to-peer connection.Type: GrantFiled: September 25, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Mark D. Tetreault
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Patent number: 12224261Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.Type: GrantFiled: September 28, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
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Patent number: 12224309Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.Type: GrantFiled: December 9, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Sou-Chi Chang, Chia-Ching Lin, Kaan Oguz, I-Cheng Tung, Uygar E. Avci, Matthew V. Metz, Ashish Verma Penumatcha, Ian A. Young, Arnab Sen Gupta
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Publication number: 20250048049Abstract: Apparatus, systems, methods, and articles of manufacture are disclosed for acoustic signal processing adaptive to microphone distances. An example system includes a microphone to convert an acoustic signal to an electrical signal and one or more processors to: estimate a distance between a source of the acoustic signal and the microphone; select a signal processing mode based on the distance; and process the electrical signal in accordance with the selected processing mode.Type: ApplicationFiled: July 19, 2024Publication date: February 6, 2025Applicant: Intel CorporationInventors: Piotr Klinke, Damian Koszewski, Przemyslaw Maziewski, Jan Banas, Kuba Lopatka, Adam Kupryjanow, Pawel Trella, Pawel Pach
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Publication number: 20250046304Abstract: A system, method and computer readable medium for dynamic noise reduction in a voice call. The system includes an encoder having a short-time Fourier transform module to determine a magnitude spectrum and a phase spectrum of an input audio signal. The input audio signal includes speech and dynamic noise. A separator is coupled to the encoder. The separator comprises a temporal convolution network (TCN) used to develop a separation mask using the magnitude spectrum as input. The TCN is trained using a frequency SNR function used to calculate loss during training. A mixer is coupled to the separator to multiply the separation mask with the magnitude spectrum to separate the speech from the dynamic noise to obtain a denoise magnitude spectrum. The system also includes a decoder coupled to the mixer and the encoder. The decoder includes an inverse short-time Fourier transform module to reconstruct the input audio signal without the dynamic noise using the denoise magnitude spectrum and the phase spectrum.Type: ApplicationFiled: July 11, 2024Publication date: February 6, 2025Applicant: Intel CorporationInventors: Adam Kupryjanow, Tomasz Noczynski, Lukasz Pindor, Sebastian Rosenkiewicz
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Publication number: 20250048088Abstract: This disclosure describes systems, methods, and devices related to sensing authorization. A device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. The device may receive an authorization response from the network based on a UE's subscription status and privacy settings. The device may execute sensing functions locally on the UE upon receiving authorization from the network. The device may transmit sensing data to the network for exposure to authorized clients. The device may update a UE's privacy profile related to sensing data via a communication with a network function.Type: ApplicationFiled: October 23, 2024Publication date: February 6, 2025Applicant: Intel CorporationInventor: Abhijeet KOLEKAR