Abstract: A method and apparatus for performing N bit by 2*N (or 2*N−1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, Ahigh and Alow respectively represent the most and least significant halves of A. According to this method, Alow is logically shifted right by one bit to generate Alow>>1. Then, Alow>>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of Ahigh times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.

Abstract: Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter. If there are any maintenance events signaled, the memory arbiter may correspondingly decrease the service period for the asynchronous request while the maintenance event is performed.

Abstract: A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.

Abstract: An electronic assembly that includes a plurality of electronic substrates that are plugged into a polygonal shaped motherboard. The polygonal shape of the motherboard minimizes the electrical path between electronic substrates while providing enough space between adjacent substrates to allow a fluid to sufficiently remove heat generated by integrated circuits of the substrates.