Patents Assigned to Intel Corpration
  • Patent number: 10860762
    Abstract: Methods and apparatus relating to subsystem-based System on Chip (SoC) integration are described. In one embodiment, logic circuitry determines one or more components of a subsystem. The subsystem supports an architectural feature to be implemented on a System on Chip (SoC) device. A first interface communicatively couples a first component of the subsystem to a first component of another subsystem. A second interface communicatively couples at least one component of the subsystem to at least one chassis component of the SoC device or communicatively couples the at least one component of the subsystem to at least one non-chassis component of the other subsystem. In an embodiment, components of the subsystem may be packaged such that the packaging generates a reusable collateral that allows for fast integration of all aspects of design in any SoC device with a compatible chassis prior to manufacture.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corpration
    Inventors: Robert P. Adler, Husnara Khan, Satish Venkatesan, Ramamurthy Sunder, Mukesh K. Mishra, Bindu Lalitha, Hassan M. Shehab, Sandhya Seshadri, Dhrubajyoti Kalita, Wendy Liu, Hanumanth Bollineni, Snehal Kharkar
  • Patent number: 6385099
    Abstract: A level shifter may be utilized in a flash memory to reduce the standby power consumption. The level shifter may be coupled so that the gate-to-source voltage of the input transistor is reduced during standby operations to reduce leakage current. At the same time, the source of the input transistor may be coupled to a lower voltage during active level shifting operations. Thus, good transistor characteristics may be achieved with reduced leakage currents.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 7, 2002
    Assignee: Intel Corpration
    Inventor: Mase J. Taub