Abstract: Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.