Patents Assigned to Intel IP Corporation
  • Patent number: 12034591
    Abstract: A base station may generate first configuration information to configure a first user equipment (“UE”) to operate using a first bandwidth within a wideband carrier of a cell, generate second configuration information to configure a second UE to operate using a second bandwidth within the wideband carrier of the cell, and cause transmission of the first and second configuration information to the first and second UEs, respectively. The base station may configure the first and second UEs based upon capabilities received from each UE, respectively.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: July 9, 2024
    Assignee: Intel IP Corporation
    Inventors: Joonyoung Cho, Gang Xiong, Ralf Bendlin, Hwan-Joon Kwon, Seunghee Han, Honglei Miao, Ingolf Karls, Markus Dominik Mueck, Michael Faerber
  • Patent number: 11798123
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20230139455
    Abstract: In one embodiment, an apparatus includes memory storing instructions and processing circuitry coupled to the memory. The processing circuitry is to implement the instructions to select a resource block group (RBG) size configuration from a set of RBG size configurations based on a bandwidth part (BWP) size. Each RBG size configuration is to indicate RBG sizes associated with respective ranges of BWP sizes, and the RBG sizes are to indicate a number of frequency-domain physical resource blocks (PRBs) for physical downlink shared channel (PDSCH) or physical uplink shared channel (PUSCH) transmissions. The processing circuitry is further to implement the instructions to allocate PRBs for communication between the gNB device and a user equipment (UE) device via the PDSCH or PUSCH transmissions based on the selected RBG size, and to encode downlink control information (DCI) that indicates the allocated PRBs for transmission to the UE device.
    Type: Application
    Filed: June 15, 2018
    Publication date: May 4, 2023
    Applicant: Intel IP Corporation
    Inventors: Debdeep Chatterjee, Sergey Panteleev, Hong He, Gang Xiong, Jeongho Jeon, Ajit Nimbalker, Joonyoung Cho
  • Publication number: 20230119093
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: August 25, 2022
    Publication date: April 20, 2023
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 11443405
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 13, 2022
    Assignee: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 11380616
    Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel IP Corporation
    Inventors: David O'Sullivan, Bernd Waidhas, Thomas Huber
  • Patent number: 11323102
    Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel IP Corporation
    Inventors: Michael Kalcher, Daniel Gruber, Francesco Conzatti, Patrizia Greco
  • Publication number: 20220013473
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 13, 2022
    Applicant: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Publication number: 20210410024
    Abstract: An apparatus of an evolved NodeB (eNB) comprises one or more baseband processors to encode measurement gap configuration information including a measurement gap configuration information element MeasGapConfig to configure a network controlled small gap (NCSG) pattern for a user equipment (UE) device if the UE requires an NCSG and the UE is not configured with a primary secondary cell (PSCELL), and a memory to store the measurement gap configuration information.
    Type: Application
    Filed: February 2, 2018
    Publication date: December 30, 2021
    Applicant: Intel IP Corporation
    Inventors: Yang Tang, Candy Yiu, Rui Huang, Jie Cui, Shuang Tian
  • Publication number: 20210368420
    Abstract: This disclosure describes systems, methods, and devices related to deterministic backoffs and collision avoidance. A device may identify a first transmission received from a first device, wherein the first transmission is over a shared access medium. The device may identify a second transmission received from the first device, wherein the second transmission is over the shared access medium. The device may determine an available transmission slot between the first transmission and the second transmission. The device may transmit, during the available transmission slot, a third transmission.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 25, 2021
    Applicant: Intel IP Corporation
    Inventors: Dave CAVALCANTI, Laurent CARIOU, Mohammad Mamunur RASHID
  • Publication number: 20210351817
    Abstract: Techniques to enable dynamic bandwidth management at the physical layer level while maintaining backwards compatibility in wireless systems is provided. Furthermore, techniques for reducing the occurrence of exposed nodes are provided. A transmitter may transmit a frame including an indication that a PHY layer sub-header defining a bandwidth associated with a channel is present. Furthermore, the transmitter may transmit a third frame after receiving a second frame from a receiver to indicate to legacy stations that the TXOP was successful.
    Type: Application
    Filed: March 24, 2021
    Publication date: November 11, 2021
    Applicant: Intel IP Corporation
    Inventors: Carlos Cordeiro, Assaf Kasher, Solomon Trainin
  • Publication number: 20210342968
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 4, 2021
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 11158585
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 26, 2021
    Assignee: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Publication number: 20210321324
    Abstract: An application management apparatus for controlling tasks, including a task split and response merge circuit configured to divide an application into a plurality of tasks and associate respective Key Performance Indicator (KPI) attributes to the plurality of tasks; and a task management circuit configured to allocate each of the plurality of tasks to a first or second Radio Access Technology (RAT) based on the KPI attributes, and to derive a plurality of task responses from the first or second RATs to which the respective plurality of tasks are allocated, wherein the task split and response merge circuit is further configured to merge the task responses to select the first or second RAT to run the application.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 14, 2021
    Applicant: Intel IP Corporation
    Inventors: Biljana Badic, Markus Dominik Mueck, Zhibin Yu, Bernhard Raaf, Dave Cavalcanti, Ana Lucia A. Pinheiro, Pinheiro
  • Publication number: 20210320071
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 14, 2021
    Applicant: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Patent number: 11128505
    Abstract: Methods, apparatuses, and computer readable media include an apparatus of an access point (AP) or station (STA) comprising processing circuitry configured to decode a legacy preamble of a physical layer (PHY) protocol data unit (PPDU), determine whether the legacy preamble comprises an indication that the PPDU is an extremely-high throughput (EHT) PPDU, and in response to the determination indicating the PPDU is the EHT PPDU, decode the EHT PPDU. Some embodiments determine a spatial stream resource allocation based on a row of a spatial configuration table, a row of a frequency resource unit table, a number of stations, and location of the station relative to the number of stations in user fields of an EHT-signal (SIG) field. To accommodate 16 spatial streams, some embodiments extend the length of the packet extension field, extend signaling of a number of spatial streams, and/or extend a number of EHT-SIG symbols.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation and Intel IP Corporation
    Inventors: Xiaogang Chen, Thomas J. Kenney, Shahrnaz Azizi, Robert J. Stacey, Laurent Cariou, Qinghua Li, Feng Jiang
  • Patent number: 11121828
    Abstract: New radio (NR) Uplink (UL) transmissions in an NR physical UL channel can be configured for a user equipment (UE) to communicate with a base station (e.g., gNB). The structures and mechanisms for configured these communications different from long term evolution (LTE) in NR specifications. A UE can generate a UL transmission with symbols on the NR physical channel including demodulation-reference signal (DM-RS) symbols and uplink control information (UCI) symbols. The UL transmissions comprise a DM-RS symbol located at each first symbol with variable lengths. The UE generates the UL transmission as an NR physical UL channel with about a 50% DM-RS overhead with a same or more DM-RS symbols than UCI symbols in a sequential pattern (e.g., an alternating pattern). The UE further maps HARQ-ACK feedback on a PUSCH based a frequency first operation that initiates following the DM-RS symbol located at the first symbol.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel IP Corporation
    Inventors: Gang Xiong, Joonyoung Cho, Lopamudra Kundu, Yongjun Kwak
  • Publication number: 20210274502
    Abstract: This disclosure describes systems, methods, and devices related to using enhanced high efficiency (HE) frames. A device may determine a high efficiency signal-B (HE-SIG-B) field for a high efficiency (HE) frame, the HE-SIG-B field comprising a common information field and a user information field. The device may determine a data portion of the HE frame, wherein the data portion includes one or more resource units (RUs) with a size equal to a number of tones. The device may determine a first resource allocation subfield and a second resource allocation subfield of the common information field based at least in part on the number of tones. The device may cause to send the HE frame.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Applicant: Intel IP Corporation
    Inventors: Xiaogang Chen, Feng Jiang, Qinghua Li, Robert Stacey
  • Publication number: 20210262864
    Abstract: An apparatus comprises: a first circuitry to charge first and second capacitors to a predetermined voltage level; a second circuitry to discharge the first capacitor through a diode at a first time; a third circuitry to discharge the second capacitor through the diode at a second time, wherein the second time is greater than the first time; a comparator to compare a first voltage of the first capacitor with a second voltage of the second capacitor; and logic to adjust a scaling factor applied to the second voltage according to an output of the comparator.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 26, 2021
    Applicant: Intel IP Corporation
    Inventor: Matthias Eberlein
  • Publication number: 20210234260
    Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include: an antenna feed substrate including an antenna feed structure, wherein the antenna feed substrate includes a ground plane, the antenna feed structure includes a first portion perpendicular to the ground plane and a second portion parallel to the ground plane, and the first portion is electrically coupled between the second portion and the first portion; and a millimeter wave antenna patch.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Applicant: Intel IP Corporation
    Inventors: Trang Thai, Sidharth Dalmia, Raanan Sover, Josef Hagn, Omer Asaf, Simon Svendsen