Patents Assigned to Intel IP Corporation
  • Patent number: 10333608
    Abstract: Apparatus, systems, and methods to implement inter-beam mobility control in MIMO communication systems are described. In one example, apparatus of an evolved Node B (eNB) comprises circuitry to configure a periodic transmit (TX) beamforming process for a user equipment (UE), wherein a plurality of different TX beams are used in a plurality of different beamforming reference signals (BRS), receive, from the UE, a selected TX beam index which identifies a selected TX beam, and schedule subsequent transmissions to the UE on the selected TX beam. Other examples are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 25, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Yushu Zhang, Yuan Zhu, Gang Xiong, Jong-Kae Fwu, Ralf Bendlin
  • Patent number: 10334511
    Abstract: Embodiments of methods for scanning in a directive multi-gigabit network are generally described herein. An apparatus of a station may include processing circuitry configured to decode a sector sweep beacon received from an access point, encode for transmission a sector sweep feedback message to include a beam refinement protocol (BRP) request, and encode for transmission BRP responses to BRP signaling received from the access point. The processing circuitry may be further configured to decode a link margin feedback signal received from the access point to determine an access point link margin, measure signal information associated with the link margin feedback signal to determine a received link margin measurement, and encode signaling for association with the access point based on the access point link quality and the receive link quality.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Solomon B. Trainin, Michael Glik, Alexander Sirotkin, Carlos Cordeiro, Elad Levy
  • Patent number: 10332821
    Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Quan Qi, Carlton E. Hanna, Eytan Mann, Sidharth Dalmia
  • Patent number: 10332871
    Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Cornelius Russ, Giuseppe Curello, Tomasz Biedrzycki, Franz Kuttner, Luis F. Giles, Bernhard Stein
  • Patent number: 10333630
    Abstract: An apparatus for reducing a magnetic coupling between a first electronic circuit and a second electronic circuit is provided. The apparatus includes a conductor loop enclosing the first electronic circuit or the second electronic circuit, and a tuning element coupled to the conductor loop. The conductor loop and the tuning element form a resonant circuit, wherein the tuning element is configured to adjust a resonance frequency of the resonant circuit to a frequency related to a frequency of a signal processed by the second electronic circuit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Stephan Leuschner, Peter Pfann
  • Patent number: 10327209
    Abstract: The disclosure relates to a baseband processing method, comprising: receiving a downlink (DL) baseband (BB) signal in a transmission time interval (TTI), wherein the DL BB signal comprises a time-frequency resource comprising a control section and a data section; decoding at least part of the control section to detect a DL grant information; if the DL grant information is detected, determine a number of granted data resource blocks from the DL grant information; and adjust at least one of a clock rate and supply voltage of the baseband processing based on the number of granted resource blocks.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Zhibin Yu, Rajarajan Balraj
  • Patent number: 10324689
    Abstract: Systems and methods for matrix-solve applications include a memory-optimized hardware acceleration (HWA) solution with scalable architecture (i.e. specialized circuitry) for HWA matrix-solve operations. The matrix-solve solutions described herein may include a scalable hardware architecture with parallel processing (e.g., “within column” processing), which provides the ability to compute several output values in parallel. The HWA matrix-solve solutions described herein may include simultaneous multi-column processing, which provides a lower execution cycle count and a reduced total number of memory accesses. This HWA matrix-solve provides a low latency and energy-efficient matrix-solve solutions, which may be used to reduce energy consumption and improve performance in various matrix-based applications, such as computer vision, SLAM, AR/VR/mixed-reality, machine learning, data analytics, and other matrix-based applications.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Gurpreet Singh Kalsi, Om Ji Omer, Dipan Kumar Mandal, Santhosh Kumar Rethinagiri, Gopi Neela
  • Patent number: 10325605
    Abstract: Techniques are provided for updating state data of an audio decoder for packet loss concealment (PLC). A methodology implementing the techniques according to an embodiment includes decoding encoded bits in a sequence of audio packets. A decoder history buffer stores the encoded bits and decimated state data associated with the decoding of those bits. The decimation factor of the state data is based on a down-sampling rate of the decoder. The method further includes performing PLC for an invalid audio packet using concealment samples from a PLC history buffer. The state of the audio decoder is updated from the decoder history buffer, based on timing associated with the concealment samples. The method further includes re-decoding the stored encoded bits associated with the updated state data, to further update the state of the audio decoder for subsequent decoding of a valid audio packet following the invalid audio packet.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 18, 2019
    Assignee: INTEL IP CORPORATION
    Inventor: Youngho Park
  • Patent number: 10325594
    Abstract: Techniques related to key phrase detection for applications such as wake on voice are discussed. Such techniques may include updating a start state based rejection model and a key phrase model based on scores of sub-phonetic units from an acoustic model to generate a rejection likelihood score and a key phrase likelihood score and determining whether received audio input is associated with a predetermined key phrase based on the rejection likelihood score and the key phrase likelihood score.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Tobias Bocklet, Joachim Hofer
  • Patent number: 10324872
    Abstract: Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Xiang Zou, Hong Wang, Gautham N. Chinya, Perry H. Wang
  • Patent number: 10326514
    Abstract: Disclosed herein are apparatuses, systems, and methods for reference signal design for initial acquisition, by receiving a first primary synchronization signal (PSS) and a first secondary synchronization signal (SSS) from a first transmit (Tx) beam, in first contiguous orthogonal frequency division multiplexing (OFDM) symbols of a downlink subframe. A UE can receive at least a second PSS and a second SSS from a second Tx beam in contiguous OFDM symbols of the downlink subframe. A UE can then detect beamforming reference signals (BRSs) corresponding to the first Tx beam and the second Tx beam, based on identification of physical cell ID information and timing information processed from the first PSS, the second PSS, the first SSS, and the second SSS. The UE can select the first Tx beam or the second Tx beam that was received with the highest power, based on the BRSs. Other embodiments are described.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Gang Xiong, Huaning Niu, Yushu Zhang, Jong-Kae Fwu, Yuan Zhu, Ralf Matthias Bendlin
  • Patent number: 10325861
    Abstract: Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventor: Giuseppe Miccoli
  • Patent number: 10327163
    Abstract: Embodiments of a UE and methods for D2D communication are generally described herein. The UE may transmit, as part of an in-network communication session, a D2D discovery status message. The D2D discovery status message may indicate an initiation or termination of a D2D discovery operation at the UE and may indicate if the UE is announcing or monitoring as part of the D2D discovery operation. The D2D discovery operation may be at least partly for configuring a D2D communication session between the UE and one or more other UEs. The UE may transmit, as part of the D2D discovery operation, a D2D discovery signal for reception at one or more other UEs. The UE may transmit and receive D2D packets over a direct link to a second UE as part of the D2D communication session.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Youn Hyoung Heo, Pingping Zong, Alexandre Saso Stojanovski, Achim Luft
  • Patent number: 10327233
    Abstract: Techniques are described for compressing the PUCCH resources reserved for acknowledging downlink data transmissions when those resources are implicitly signaled by EPDCCHs that schedule the downlink transmissions in TDD mode. An acknowledgement resource offset field transmitted in the EPDCCH is configured to correspond to one or more values that compress the region in PUCCH resource index space that would otherwise be reserved for the subframes of a bundling window.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Seunghee Han, Yuan Zhu, Xiaogang Chen, Jong-Kae Fwu
  • Patent number: 10327143
    Abstract: Some demonstrative embodiments include devices, systems and/or methods of communicating between a cellular manager and a User Equipment (UE) via a Wireless Local Area network (WLAN) node. For example, an Evolved Node B (eNB) may be configured to communicate with a User Equipment (UE) traffic of at least one Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) Radio Access Bearer (E-RAB); to participate in establishment of an IP tunnel with the UE via a Wireless Local Area Network (WLAN) node; to encapsulate an IP payload comprising downlink traffic of the E-RAB in an IP tunneling packet; and to send the IP tunneling packet to the UE via the IP tunnel.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 18, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Alexander Sirotkin, Nageen Himayat, Farid Adrangi
  • Patent number: 10327216
    Abstract: Methods and devices for performing a page synchronization of a communication signal having a page structure with at least one repeating feature, the methods and devices configured to demodulate the communication signal to produce a raw symbol stream; correlate a plurality of subsets of the raw symbol stream with a page synchronization pattern; detect which of the plurality of subsets meet a pre-determined correlation condition; and identify two of the detected subsets based on a characteristic of the at least one repeating feature.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL IP CORPORATION
    Inventor: Vinay Simha
  • Publication number: 20190182696
    Abstract: New radio (NR), also known as fifth generation (5G) radio or fifth generation long term evolution (5G LTE)) uses a measurement gap that allows for measurement on different beams, multiple frame structure and inter-radio access technology measurement. For example, in measurement on the different beams, the UE (114) and eNB (304) beam sweep (i.e., change analog beam transmitter). The UE (114) can measure different beams from a fifth generation node B (gNB) and/or other RAN nodes. The measurement gap can be used for intrafrequency/interfrequency measurement when beam specific reference signals (BRSs) are not transmitted in the same subframe. A multiple frame structure can use the specific measurement configuration to utilize the beam resources efficiently. LTE and NR and other interRAT measurement can also use the measurement gap.
    Type: Application
    Filed: June 29, 2017
    Publication date: June 13, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Rui Huang, Yang Tang, Candy Yiu
  • Publication number: 20190182009
    Abstract: Described is an apparatus of a first User Equipment (UE) operable to communicate with on a wireless network. The apparatus may comprise a first circuitry, and a second circuitry. The first circuitry may be operable to establish a parameter set defining 5G Physical Downlink Control Channel (xPDCCH) transmission to the UE. The second circuitry may be operable to generate, for transmission to the UE, one or more messages including the parameter set.
    Type: Application
    Filed: September 14, 2017
    Publication date: June 13, 2019
    Applicant: Intel IP Corporation
    Inventors: Bishwarup Mondal, Ajit Nimbalker, Gang Xiong, Peng Lu, Jong-Kae Fwu
  • Publication number: 20190182824
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus of a machine-type communication (MTC) user equipment (UE) comprises baseband processing circuitry to establish a radio resource control (RRC) connection with an evolved Node B (eNB), and process a message from the eNB indicating a number of repetitions of physical uplink control channel (PUCCH) transmissions to be used over multiple uplink subframes after the radio resource control connection is established.
    Type: Application
    Filed: March 31, 2016
    Publication date: June 13, 2019
    Applicant: Intel IP Corporation
    Inventor: Debdeep Chatterjee
  • Patent number: 10321486
    Abstract: Methods and devices are described for providing wireless stations (STAs) with two sets of enhanced distributed channel access (EDCA) parameters. Legacy EDCA parameters that are for single user (SU) operations and may be used by both high-efficiency (HE) STAs and legacy STAs without multi-user (MU) capability. MU EDCA parameters are defined to be more restrictive than legacy EDCA parameters in favoring MU operations. Embodiments are described that define sets of rules for regulating how STAs capable of both SU and MU uplink operations can use the different sets of EDCA parameters.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel IP Corporation
    Inventors: Laurent Cariou, Po-Kai Huang, Chittabrata Ghosh, Robert J. Stacey