Patents Assigned to Intel IP Corporation
  • Patent number: 10733697
    Abstract: An apparatus for applying a convolutional neural network (CNN) to a wide-angle camera image is described herein. The apparatus includes a camera, controller, convolution mechanism and a fully connected layer. The camera is to capture a wide-angle image, and the controller is to map the image on a 3D surface. The convolution mechanism is to perform convolution on the 3D surface and the fully connected layer is to classify a plurality of features generated by the convolution mechanism.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel IP Corporation
    Inventors: Koba Natroshvili, Kay-Ulrich Scholl
  • Patent number: 10735960
    Abstract: Methods and systems for authenticated wake-up radio frames are disclosed. In one aspect, a method includes generating a wake-up radio (WUR) integrity group key (IGTK) for authentication of WUR frames when received by a wake-up radio (WURx). The WUR IGTK may be identified via a key identifier in the WUR frame. The key identifier may be updated when the WUR IGTK is updated, facilitating WUR IGTK key updating across multiple associated stations.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation and Intel IP Corporation
    Inventors: Po-Kai Huang, Shahrnaz Azizi, Daniel F. Bravo, Ido Ouzieli, Emily H. Qi, Noam Ginsburg, Robert J. Stacey
  • Patent number: 10724854
    Abstract: An occupancy grid object determining device is provided, which may include a grid generator configured to generate an occupancy grid of a predetermined region, the occupancy grid including a plurality of grid cells and at least some of the grid cells having been assigned an information about the occupancy of the region represented by the respective grid cell, a determiner configured to determine at least one object in the occupancy grid wherein the at least one object includes a plurality of grid cells, and a remover configured to remove occupancy information from at least one grid cell of the plurality of grid cells of the determined object.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Koba Natroshvili, Kay-Ulrich Scholl
  • Patent number: 10728750
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communication over a 6 Gigahertz (GHz) wireless frequency band. For example, an apparatus may be configured to cause a licensed 6 GHz wireless communication device, which is licensed by a regulatory authority to communicate over a wireless communication channel in the 6 GHz wireless frequency band, to detect in a transmission over the wireless communication channel in the 6 GHz wireless frequency band an identifier of an unlicensed 6 GHz wireless communication station (STA), which is not licensed by the regulatory authority to communicate over the 6 GHz wireless frequency band; and to send a report comprising the identifier of the unlicensed 6 GHz STA.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 28, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Laurent Cariou, Robert Stacey, Thomas J. Kenney, Yaron Alpert, Ehud Reshef
  • Patent number: 10725468
    Abstract: Herein is disclosed a bounding-volume based unmanned aerial vehicle illumination management system comprising one or more processors, configured to define a plurality of bounding volumes within a region of unmanned aerial vehicle flight; determine a subset of unmanned aerial vehicles within a bounding volume according to an unmanned aerial vehicle flight plan; determine a combined lighting value of the subset of unmanned aerial vehicles according to an unmanned aerial vehicle illumination plan; and determine a surface illumination corresponding to the combined lighting value of one or more bounding volumes.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP corporation
    Inventor: Daniel Pohl
  • Patent number: 10728856
    Abstract: Logic may implement protocols and procedures to suspend a wake-up radio mode. Logic may enter a wake-up radio (WUR) mode suspend with a WUR request indicative of the WUR mode suspend. Logic may enter the WUR mode suspend from a WUR mode with a one-way handshake and may exit from the WUR mode to the WUR mode suspend. Logic may negotiate WUR mode parameters without entering the WUR mode. Logic may default to a WUR mode or a WUR mode suspend in response to receipt of a wake-up packet. Logic may receive the WUR request frame with a WUR mode suspend field to request entry into a WUR mode suspend. Furthermore, logic may maintain negotiated WUR mode parameters during the WUR mode suspend.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 28, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Po-Kai Huang, Noam Ginsburg, Daniel F. Bravo
  • Patent number: 10727197
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Wolter, Thomas Wagner, Stephan Stoeckl, Laurent Millou
  • Publication number: 20200236572
    Abstract: Systems, methods, and apparatuses may configure a measurement gap per frequency group and per cell. Measurement time and frequency resources may be associated with a carrier frequency, a cell, or both. Thus, a user equipment (UE) may determine the measurement configuration based on the carrier frequency, cell, or both.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 23, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Candy Yiu, Jie Cui, Yang Tang
  • Patent number: 10720393
    Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas
  • Patent number: 10718812
    Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
  • Patent number: 10721314
    Abstract: Certain embodiments herein are directed to enabling service interoperability functionality for wireless fidelity (WiFi) Direct devices connected to a network via a wireless access point. A WiFi Direct device may identify various other WiFi Direct devices on a WiFi network for performing a requested service, such as printing content or displaying content to a screen. In so doing, the device may share information associated with an access point to which the device is connected with the other devices, which may also share information associated with an access point to which they are connected. In this way, WiFi Direct devices may discover their connectivity with respect to other devices to utilize a broader array of connection options for implementing a desired service, and hence, may leverage application programming interface (API) modules directed at providing service interoperability functionality between software applications and services requested by the software applications.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Emily H. Qi, Carlos Cordeiro, Ganesh Venkatesan, Bahareh Sadeghi
  • Patent number: 10721761
    Abstract: Computer readable media, methods, and apparatuses for centralized channel access for primary and secondary channels are disclosed. An apparatus is disclosed comprising memory and processing circuitry. The processing circuitry is configured to encode a schedule of one or more resource allocations, wherein each resource allocation comprises a type of allocation, a bandwidth, an indication of a channel, a source association identification (AID), a destination AID, an allocation start, and a duration. The type of allocation may be a service period (SP) or a contention-based access period (CBAP). The channel may be an indication of a basic service set (BSS) or a personal BSS (PBSS) primary channel, BSS or PBSS secondary channel, or BSS or PBSS tertiary channel. The processing circuitry may be configured to transmit the schedule to one or more stations identified by the source AID and the destination AID of the one or more resource allocations.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Laurent Cariou, Carlos Cordeiro, Chittabrata Ghosh, Assaf Kasher, Solomon B. Trainin
  • Patent number: 10721786
    Abstract: A network communication device comprises physical layer (PHY) circuitry configured to transmit and receive radio frequency electrical signals to communicate directly with one or more separate network devices; and medium access control layer (MAC) circuitry. The MAC circuitry is configured to: initiate transmission of a packetized message that includes a neighbor awareness networking (NAN) public action frame; receive a data connection request message from a second network device that includes one or more quality of service (QoS) requirements; initiate transmission of a data connection response message that includes data exchange time window information and channel information; and communicate data device-to-device with the second network device according to the data exchange time window information and channel information.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Dibakar Das, Po-Kai Huang, Elad Oren, Emily H. Qi, Minyoung Park
  • Publication number: 20200228141
    Abstract: For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Artyom Lomayev, Alexander Maltsev, Michael Genossar, Claudio Da Silva, Carlos Cordeiro
  • Publication number: 20200228224
    Abstract: An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDPC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.
    Type: Application
    Filed: June 21, 2018
    Publication date: July 16, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Alexander Maltsev, Carlos Cordeiro, Artyom Lomayev, Michael Genossar, Claudio Da Silva
  • Publication number: 20200228241
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi-Gigabit (DMG) (EDMG) Orthogonal Frequency-Division Multiplexing (OFDM) Physical layer (PHY) Protocol Data Unit (PPDU). For example, an EDMG station (STA) may be configured to generate an EDMG OFDM PPDU including at least a non-EDMG header (L-Header), an EDMG header, and a data field, the EDMG header including a spoofing error length indicator field configured to indicate whether or not a spoofing error of the EDMG OFDM PPDU is less than one OFDM symbol duration; and to transmit the EDMG OFDM PPDU over a channel bandwidth in a frequency band above 45 Gigahertz (GHz).
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Claudio Da Silva, Artyom Lomayev, Alexander Maltsev, Carlos Cordeiro, Michael Genossar
  • Publication number: 20200228294
    Abstract: For example, an EDMG STA may be configured to receive an A-MPDU for the EDMG STA in an EDMG MU PPDU from an EDMG MU-MIMO initiator station; to determine, according to an ordered acknowledgement scheme, a Block Acknowledgement (BA) period in which the EDMG STA is to be awake to allow transmission of a BA from the EDMG STA to the EDMG MU-MIMO initiator STA; to allow the EDMG STA to be in a power save mode during a first power save period from a time of an End of Frame (EOF) field in the A-MPDU for the EDMG STA until a beginning of the BA period; to transmit the BA to the EDMG MU-MIMO initiator; and to allow the EDMG STA to be in the power save mode during a second power save period after transmission of the BA.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Cheng Chen, Carlos Cordeiro, Claudio Da Silva, Oren Kedem
  • Publication number: 20200228140
    Abstract: For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) may be configured to scramble, according to a first scrambling sequence, a plurality of EDMG Header B bits of an EDMG Header B field of an EDMG Multi-User (MU) Physical Layer (PHY) Protocol Data Unit (PPDU) into a plurality of scrambled header bits; generate a Low-Density Parity-Check (LDPC) codeword based on the plurality of scrambled header bits; determine a data block based on the LDPC codeword; generate one or more scrambled data blocks based on the data block by scrambling the data block according to a second scrambling sequence; and transmit a wireless transmission of the EDMG Header B based on the one or more scrambled data blocks.
    Type: Application
    Filed: June 18, 2018
    Publication date: July 16, 2020
    Applicant: INTEL IP CORPORATION
    Inventors: Artyom Lomayev, Alexander Maltsev, Michael Genossar, Claudio Da Silva, Carlos Cordeiro
  • Patent number: 10715995
    Abstract: Methods, apparatus, and computer-readable media are described to encode a trigger frame for a second station (STA2). A first sounding frame for the STA2 is generated. The first timestamp is associated with a transmission of the first sounding frame. A second sounding frame from the STA2 based upon the first sounding frame is decoded. The second sounding frame includes a holding time indication associated with a second timestamp and a third timestamp. A fourth timestamp is associated with receiving the second sound frame. The holding time indication is protected. A round-trip time is calculated based upon the first timestamp, the holding time indication, and the fourth timestamp.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Jonathan Segev, Qinghua Li, Benny Abramovsky, Feng Jiang
  • Patent number: 10714455
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber