Abstract: A self-calibration circuit and associated method for testing an RF device includes the RF device to be tested having transmit and receive sections, and a built-in self test (BIST) circuit coupled to the transmit and receive sections of the RF device on the same chip. The self-calibration circuit is configured to calibrate the receive section of the RF device in a receive test mode, and calibrate the transmit section of the RF device in a subsequent transmit test mode using the calibrated receive section to measure a transmit output signal from the transmit section and to provide calibration data therefrom used in the transmit section calibration. The self-calibration circuit may include a duplex filter coupled between the transmit and receive sections and the BIST circuit, and a multiplexor coupled between the RF device, and the BIST circuit, configured to select one or more of a plurality of RF devices to be tested.
Abstract: The switched-mode power supply includes a power stage, and a control unit to control the operation of the power stage based on a critical parameter of the power stage, wherein the control unit is configured to control the operation of the power stage to change from a first operational mode to a second operation mode if the critical parameter leaves a pre-defined range, and to change from the second operational mode to the first operational mode based on a measurement of a first time interval.
Abstract: A communication device may be provided. The communication device may include: a requester to request information indicating communication devices that provide pre-determined data; a receiver to receive the information indicating communication devices that provide the pre-determined data; a determiner to determine a download target based on the information indicating communication devices that provide the pre-determined data; and a transmitter to transmit information indicating the determined download target for a peer-to-peer communication of the pre-determined data from the download target.
Abstract: A digital filter converts a digital input sequence into a digital output sequence. The digital filter includes an integrator stage having a plurality of closed-loop controlled time-delay elements. The integrator stage is configured to have each closed-loop controlled time-delay element set to a value which is predetermined for the respective closed-loop controlled time-delay element. The digital filter includes a further stage. The integrator stage and the further stage are configured to operate at different clock frequencies.
Abstract: An electrical circuit includes a circuit element and a common mode rejection circuit element. The circuit element is configured to operate at a selected frequency within a variable frequency range and the common mode rejection circuit element is configured to reject a common mode current through the circuit element, wherein the common mode rejection circuit element is adjustable.
Abstract: An implementation relates to compensating DC offset in a signal path. The signal path may have a plurality of stages, where for each stage a fine DC compensation is performed by introducing a fine DC compensation signal into the signal path of the stage by way of a compensation analog to digital converter.
Abstract: A method, system, and apparatus is provided for interference calibration. A second mobile terminal may be configured to send timing information to a network interface in an uplink channel of a second communication system. The network interface may be configured to communicate with a first mobile terminal in a downlink channel in a first communication system; estimate the uplink channel using the timing information to form a channel estimation; and adjust the downlink channel to the first mobile terminal using the channel estimation.
Type:
Grant
Filed:
May 31, 2012
Date of Patent:
July 8, 2014
Assignee:
Intel Mobile Communications GmbH
Inventors:
Irfan Ghauri, Francesco Negro, Dirk Slock
Abstract: A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.
Abstract: A method includes receiving a signal including first data precoded on the basis of a first codebook entry of a codebook, wherein the codebook includes at least one further codebook entry, averaging a set of matrices to obtain a mean matrix wherein each matrix of the set of matrices is determined on the basis of a respective other codebook entry of the at least one further codebook entry and determining a covariance matrix on the basis of the mean matrix.
Abstract: A signal processing circuit for providing a modulated analog transmit signal on the basis of a digital transmit data signal is configured to vary a resolution in dependence on a detected or predefined parameter when providing the modulated analog transmit signal.
Abstract: A device for reducing an error signal component of a transmit signal in a receive signal, including an interface, a transmit signal generator, a transmitting/receiving device, a correction signal generator and a combiner. The combiner is configured to combine the receive signal with a correction signal from the correction signal generator in order to reduce the proportion that is based on the known wideband error signal component of the transmit signal in the receive signal.
Abstract: A signal processing device for providing first and second analog signals includes first and second clocked digital signal path circuits and a transit time difference measuring device. The first clocked digital signal path circuit is configured to yield first digital data for providing a first analog signal. The second clocked digital signal path circuit is configured to yield second digital data for providing the second analog signal. The transit time difference measuring device is configured to yield a transit time difference measuring signal describing a difference between a signal transit time along a first measuring path and a signal transit time along a second measuring path, with the first measuring path including a first clock supply allocated to the first clocked digital signal path circuit, and with the second measuring path including a second clock supply allocated to the second clocked digital signal path circuit.
Abstract: An analog-to-digital converter for converting an input signal includes a sigma-delta modulator for receiving an analog modulator input signal and for providing a digital modulator output signal and an interference cancellation loop. The interference cancellation loop includes a digital filter, a digital-to-analog converter, and a signal combiner. The digital filter is configured to amplify the sigma-delta output signal in a frequency band, attenuate the sigma-delta output signal outside the frequency band and a transition band surrounding the frequency band, and provide a filtered digital feedback signal. The digital-to-analog converter is configured to convert the filtered digital signal to a cancellation signal. The signal combiner is configured to combine the input signal with the cancellation signal resulting in the modulator input signal, in order to at least partially cancel interference signal portions within the input signal.
Type:
Grant
Filed:
January 31, 2012
Date of Patent:
June 24, 2014
Assignee:
Intel Mobile Communications GmbH
Inventors:
Rudolf Ritter, Markus Schimper, Werner Schelmbauer, Maurits Ortsmanns
Abstract: A communication terminal into which communication data can be input and which can receive a message signalling that at least one further communication terminal is ready to receive the communication data. Following receipt of the message, a transmission device configured to operate in a first mode, in which it sends data at a first data rate, and in a second mode, in which it sends data at a second data rate, which is higher than the first data rate, is used to send the communication data in the second mode.
Abstract: A method, an apparatus and a communication unit for generating precoding feedback information in a multiple frequency radio transmission system are disclosed. A rank for precoding matrices, wherein the rank is constant over the multiple frequencies, is selected and a plurality of precoding matrices having the selected rank are selected. A different precoding matrix is selected for each frequency subset of the multiple frequencies.
Abstract: A transmit circuit includes a power amplifier configured to amplify an RF input signal to obtain an RF output signal, and an antenna tuner configured to transform an antenna impedance to an impedance at an input of the antenna tuner, wherein the input of the antenna tuner is coupled to an output of the power amplifier. The transmit circuit further includes a bias controller configured to control a bias of the power amplifier, wherein the bias controller is configured to provide a bias control signal to adjust the bias of the power amplifier based on a determination of a measure of a load impedance provided to the power amplifier by the antenna tuner.
Abstract: One embodiment of the present invention relates to an apparatus for preventing remodulation in a transmission chain. A first offset generation circuit selectively introduces a first frequency offset into in-phase (I) and quadrature phase (Q) equivalent baseband signals. A second offset generation circuit selectively introduces a second frequency offset into an oscillator output signal. The frequency of the offset oscillator output signal is divided by a divider to form offset local oscillator signals, which are provided to up-conversion mixers that modulate the offset equivalent baseband signals onto the offset local oscillator signals to generate a composite modulated output signal. The first and second frequency offsets are chosen to have values that cancel during modulation. However, because the second frequency offset shifts the offset oscillator output signal's frequency to a value that is no longer a harmonic of the composite modulated output signal's frequency, remodulation is prevented.
Abstract: An amplifier includes an amplifying stage configured to provide an amplifier output signal based on a combination of a received amplifying stage input signal and a received amplified version of the amplifying stage input signal.
Abstract: A communication device is described including a receiver, a determiner configured to determine, for a first data transmission via a first communication channel and a second data transmission via a second data communication channel, wherein the first data transmission and the second data transmission overlap in time, a first time period during which the receiver is to receive data transmitted in the first data transmission and a second time period during which the receiver is to receive data transmitted in the second data transmission based on information about the quality of data transmission via the first communication channel and based on information about the quality of data transmission via the second communication channel and a controller configured to control the receiver to receive data transmitted in the first data transmission during the first time period and to receive data transmitted in the second data transmission during the second time period.