Abstract: Data characters having a given number of bits are encoded in individual linear arrays transverse to a scanning path and spaced apart along said path for successive readout by a reading head scanning said path. Index bits, all having logical 1, i.e., mark, significance, are disposed in separate linear arrays parallel to and adjacent each character. The scanning head has at least 2x pairs of sensors consisting each of an index and a data sensor where x equals the number of bits in a character. The geometry in one embodiment is such that at least two adjacent sensor pairs scan each data bit and at least one unused sensor pair is between sensor pairs responding to adjacent bits in a character. Electronic logic sorts the signals obtained from the sensors, in spite of varying registration and skew, during a scan of said path to enter the bits of alternate characters in respective alternate memory banks.