Abstract: This invention relates to embedded processing systems used for industrial, commercial, and medical automated systems in which microprocessors or digital signal processors are employed to perform a plurality of distinct tasks based on real-time events and conditions. In particular, this invention provides an efficient processing system and environment in which a variety of application threads may share the processing bandwidth and system resources cooperatively and efficiently, with minimized coupling of the application threads to each other and system resource control details.

Abstract: A multi-processor system includes a global bus (14) with a global address space and a plurality of processor nodes (10). Each of the processor nodes (10) has a CPU (20) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) (34) is provided for interfacing between the global bus (14) and the local bus (30). Each DPSRAM (34) for each processor core (10) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node (10), it is only necessary to address the designated DPSRAM (34) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU (20) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM (34). This results in only a single access cycle for data transfer. Each of the CPU's (20) can communicate directly with another of the CPU's (20) through an interprocessor communication network.

Abstract: A multi-processor system includes a global bus (14) having associated therewith a global address space with a plurality of processor nodes (10) associated therewith. Each of the processor nodes (10) has a CPU (20) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus (14) has associated therewith an arbiter (412). Each of the processing nodes interfaces with a global register (410) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter (412) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.

Abstract: The inventive system provides a set of human input and output devices such as a video monitor and keyboard, in conjunction with a processing means such as a Personal Computer, an in-circuit microprocessor emulation means, and control software which allows a software developer to interactively and intelligently view the contents of bit-mapped hardware control and status registers in a descriptive manner. Further, the system interacts with the in-circuit emulator and code development environment to automatically create hexadecimal representations of complete register values to be read and written, and performs validity rule checking in order to notify the software developer if disallowed combinations of bit fields have been selected.

Abstract: The inventive embedded processing subsystem module is adapted for backside circuit board assembly directly opposite of a specific microprocessor or Digital Signal Processor so that circuit groups such as memory banks and communications peripherals may utilize otherwise unused backside printed circuit board space underneath the processor device, and further so that high-speed signals interconnecting the processor and subsystem circuit devices traverse a minimized printed circuit track length.

Abstract: The inventive embedded processing subsystem module is adapted for backside circuit board assembly directly opposite of a specific microprocessor or Digital Signal Processor so that circuit groups such as memory banks and communications peripherals may utilize otherwise unused backside printed circuit board space underneath the processor device, and further so that high-speed signals interconnecting the processor and subsystem circuit devices traverse a minimized printed circuit track length.

Abstract: The inventive system and method provides a processing resource which performs bit reversing and Boolean algebraic operations. These operations are commonly needed by discrete transform algorithms to reorder data samples. By selectively remapping the address bus, a series of non-linear accesses to the data memory are converted to linear accesses. Another use of the invention to pack floating point numbers in memory is also disclosed. An embodiment using an in-circuit reprogrammable logic device is disclosed which allows processing software to dynamically reconfigure the mapping logic and rules.

Abstract: A system and method for multi-channel data management with dynamically configurable routing, having multiple independent container instances or crossbars. The system and method provide dynamically allocated and released half- and full-duplex data communications channels through crossbar access ports, with intercommunications between transmit ports and receive ports being independently configured. Transmission and reception of data is provided through the reserving of pages of transmission media, allocation of pages to producers of data, transmission of the filled pages to a queue for reception at one or more receiving ports, and reception by a consumer through a receiving port. Allocation, transmission and reception of the pages may optionally be executed synchronous to the availability of the page. Page state changes are used to mark pages as to their availability, allocation, and queuing such that data transfer is accomplished using an in-place method.

Abstract: By coupling the functionality of an Internet Telephony function in a personal computer, an Internet Voice Gateway, and a small-office/home-office (SOHO) private branch exchange (PBX), and through inventive coordination of the functions of these units, a SOHO telecommunications system and method are realized which allow use of PBX extension telephones while all PBX outbound telephone lines are occupied by Internet data communications sessions.