Patents Assigned to Intellectual Business Machines Corporation
  • Patent number: 8612867
    Abstract: A computer implemented method, system and/or computer program product automatically extends a collaboration window. An initiation of an interactive teleconference, which utilizes a collaboration window that is displayed on two communication devices, is detected. The topic of the interactive teleconference is determined by a starting context of the interactive teleconference. The topic is associated with a related application that provides supporting information for the interactive teleconference. This supporting information and/or associated application(s) are then displayed on one or both of the two communication devices.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: December 17, 2013
    Assignee: Intellectual Business Machines Corporation
    Inventors: Josef Scherpa, Andrew L. Schirmer
  • Patent number: 8473602
    Abstract: Systems and methods are provided to determine an allocation of network resources in a distributed on-demand information technology (IT) systems using existing control mechanisms for other operating system resources in order to achieve a desired operating point within the IT system. This desired operating point is obtained by optimizing a goal-based objective function while taking into account system constraints. The relationship between utilization of all system resources, i.e. network resources and processing resources, and attainment of performance objectives is autonomously obtained for a plurality of actions that could be required by a range of system applications. This relationship is used to allocate network resources to applications while maintaining desired performance objectives. The allocation is enforced using existing control mechanisms.
    Type: Grant
    Filed: June 11, 2005
    Date of Patent: June 25, 2013
    Assignee: Intellectual Business Machines Corporation
    Inventors: Zhen Liu, Dimitrios Pendarakis, Jeremy I. Silber, Laura Wynter
  • Publication number: 20100248424
    Abstract: A first semiconductor chip and a second semiconductor chip are provided with a matching pair of hydrophilic top surfaces each including a matched set of conductive contact structures. In one embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a mesa of which the periphery coincides with the shape of a hydrophilic top surface. In another embodiment, the first semiconductor chip, the second semiconductor chip, or both is provided with a peripheral hydrophobic top surface that laterally surrounds a hydrophilic top surface. Prior to vertical stacking, a polar liquid coats the hydrophilic top surface of a first semiconductor chip. When a second semiconductor chip is placed on the polar liquid, the matching shapes of two hydrophilic surfaces are self-aligned by moving the second semiconductor chip as needed.
    Type: Application
    Filed: December 10, 2009
    Publication date: September 30, 2010
    Applicant: Intellectual Business Machines Corporation
    Inventors: Stephen E. Luce, Anthony K. Stamper
  • Patent number: 6890599
    Abstract: New etch barriers of indium-tin-oxide in the manufacturing process of thin film transistor-liquid crystal display are self-assembled monolayers, such as n-alkylsilanes. A typical process of applying a self-assembled monolayer is to ink a hydrolyzed n-octadecyltrimethoxysilane solution on to a stamp and then to transfer the solution onto ITO. The surface of the stamp may be polar enough to be wet with polar self-assembled monolayer solutions of an akylsilane. A non-polar stamp surface may be treated with oxygen plasma to obtain a wettable polar surface.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: May 10, 2005
    Assignee: Intellectual Business Machines Corporation
    Inventors: Stephen L. Buchwalter, Gareth Geoffrey Hougham, Kang-Wook Lee, John J. Ritsko, Mary Elizabeth Rothwell, Peter M. Fryer
  • Patent number: 5737751
    Abstract: A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: April 7, 1998
    Assignees: Intellectual Business Machines Corporation, Motorola, Inc.
    Inventors: Rajesh Bhikhubhai Patel, Sung-Ho Park, Romesh Mangho Jessani, Belliappa Manavattira Kuttanna