Abstract: An active pixel sensor includes a photosensitive device and a dynamic comparator that when coupled with a voltage ramp will form a digital pixel sensor with pulse width modulated digital output. A number of switches are included in the digital pixel sensor to configure the input of the dynamic comparator to couple with the photosensitive device or the voltage ramp such that the dynamic comparator is free from input transistor mismatch problem, as both input use the same input transistor. A cascade of dynamic comparator is disclosed in this invention, such as to improve the sensitivity and conversion speed of the digital pixel sensor. There are a number of switches that connect and isolate the digital pixel sensor from the bit line, which is shared by a plurality of digital pixel sensors in the sensor array. Photosensitive devices in close proximity can share the dynamic comparator by a number of selection switches, such that each photosensitive device can be read out in a time shared manner.

Abstract: An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.

Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.