Abstract: Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change.
Type:
Application
Filed:
December 5, 2008
Publication date:
June 10, 2010
Applicant:
Intellectual Ventures Management, LLC
Inventors:
Doug Burger, Stephen W. Keckler, Changkyu Kim
Abstract: The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
Type:
Application
Filed:
December 5, 2008
Publication date:
June 10, 2010
Applicant:
Intellectual Ventures Management, LLC
Inventors:
Doug Burger, Stephen W. Keckler, Nitya Ranganathan