Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.