Patents Assigned to Intemational Business Machines Corporation
  • Patent number: 11144213
    Abstract: A metadata track stores metadata corresponding to both a first customer data track and a second customer data track. In response to receiving a first request to perform a write on the first customer data track from a two track write process, exclusive access to the first customer data track is provided to the first request, and shared access to the metadata track is provided to the first request. In response to receiving a second request to perform a write on the second customer data track from the two track write process, exclusive access to the second customer data track is provided to the second request, and shared access to the metadata track is provided to the second request prior to providing exclusive access to the metadata track to at least one process that is waiting for exclusive access to the metadata track.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Intemational Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Jared M. Minch, Beth A. Peterson
  • Patent number: 10362716
    Abstract: A configurable door panel cover includes a first face of a first door that is perforated and includes one or more attachment points, which one or more configurable panels may attach to. The configurable door panel cover includes a fastener assembly that includes at least one fastener that attaches to the configurable door panel cover, and a spacing mechanism. The spacing mechanism attaches to the fastener that is attached to the configurable door panel cover and to one of the one or more attachment points on the first face of the first door. The spacing mechanism attaches the first configurable door panel cover at a first orientation that includes a first angle between the configurable door panel cover and the first spacing mechanism. The fastener assembly may be rotated to the configurable door panel cover.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 23, 2019
    Assignee: Intemational Business Machines Corporation
    Inventors: Paula Besterman, Aaron R. Cox, Camillo Sassano, Kevin L. Schultz
  • Publication number: 20150270373
    Abstract: A replacement metal gate process which includes forming a fin on a semiconductor substrate; forming a dummy gate structure on the fin; removing the dummy gate structure to leave an opening that is to be filled with a permanent gate structure; depositing a high dielectric constant (high-k) dielectric material in the opening and over the fin; depositing a work function metal in the opening and over the fin so as to be in contact with the high-k dielectric material, the high k dielectric material and the work function metal only partially filling the opening; filling a remainder of the opening with an organic material; etching the organic material until it is partially removed from the opening; etching the work function metal until it is at a same level as the organic material; removing the organic material; and filling the opening with a metal until the opening is completely filled.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: Intemational Business Machines Corporation
    Inventors: David V. Horak, Effendi Leobandung, Stefan Schmitz, Junli Wang
  • Publication number: 20150054082
    Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 26, 2015
    Applicant: Intemational Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthi Haran, Junjun Li, Shom Ponoth, Theodorus Eduardus Standaert, Tenko Yamashita
  • Publication number: 20150056792
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Applicant: Intemational Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140325514
    Abstract: A solution is proposed for maintaining virtual machines being available in a data-processing system. A mechanism determines a list of software components installed on each virtual machine, retrieves a set of maintenance policies for each software component, each maintenance policy being indicative of a patch to be applied to the corresponding software component. The mechanism determines a set of old virtual machines having at least one old software component thereof requiring the application of at least a new one of the corresponding patches according to a comparison among the maintenance policies and a maintenance register indicative of a current state of the software components of the virtual machines. The mechanism applies the corresponding at least one new patch to each old software component of each old virtual machine and updates the maintenance register according to the application of said at least one new patch to each old software component of each old virtual machine.
    Type: Application
    Filed: December 4, 2012
    Publication date: October 30, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Fabio Benedetti, Jacques Fontignie, Claudio Marinelli, Luigi Pichetti
  • Publication number: 20140175374
    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.
    Type: Application
    Filed: March 2, 2014
    Publication date: June 26, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140175375
    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.
    Type: Application
    Filed: March 2, 2014
    Publication date: June 26, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140013235
    Abstract: A method, computer program product, and system for a quality-of-service history database is described. A first input associated with a change to a component of a graphical user interface is received, wherein a portion of the component is represented as a first node of a tree structure representing a portion of the graphical user interface. A first characteristic of the change is determined. The first characteristic of the change is associated with a second node of the topic tree structure. The associated first characteristic is transmitted to a first computing device, wherein transmission of the associated first characteristic allows one or more of the first computing device and a second computing device to determine a first aspect of the change based upon, at least in part, the topic tree structure.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: Intemational Business Machines Corporation
    Inventors: Steven John Horsman, Matthew John Kockott, Jonathan Christopher Mace, Andrew Moger
  • Publication number: 20130097611
    Abstract: A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized.
    Type: Application
    Filed: December 8, 2012
    Publication date: April 18, 2013
    Applicant: Intemational Business Machines Corporation
    Inventor: Intemational Business Machines Corporation
  • Publication number: 20090109780
    Abstract: A hybrid circuit for a memory includes: a skewed static logic gate circuit; a dynamic pre-discharge device coupled with the skewed static logic gate circuit for operating the static logic gate circuit as a dynamic circuit.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Applicant: Intemational Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye, Yutaka Nakamura
  • Publication number: 20080023789
    Abstract: The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.
    Type: Application
    Filed: August 7, 2007
    Publication date: January 31, 2008
    Applicant: Intemational Business Machines Corporation
    Inventors: Louis Hsu, Conal Murray, Chaudrasekhar Narayan, Chih-Chao Yang