Abstract: Devices and systems with interposers that do not include through-substrate vias, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes an interposer and one or more integrated circuit (IC) dies coupled to the interposer. The interposer includes one or more conductive traces and one or more vias, but the interposer does not include through-substrate vias. The respective IC dies are electrically coupled to the interposer via dielectric-to-dielectric and metal-to-metal bonds at the interface between the interposer and the respective IC dies.

Abstract: A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.

Abstract: An area-efficient delay cell utilizes transistor stacks to control positive feedback responsive to a counter code, thereby controlling the hysteresis and overall signal delay of the cell. The code-delay response of the cell can be modified by freezing the counter code at a convenient value. Linear superposition of the responses of one modified cell connected in series with one unmodified cell provides a more linear overall response and reduces jitter when used in a delay locked loop.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.