Abstract: An interconnect device includes a data switch and a control switch coupled in parallel between multiple input lines and a plurality of output ports. The interconnect device comprises an input logic element coupled between the multiple input lines and the data switch. The input logic element can receive a data stream composed of ordered data segments, insert the data segments into the data switch, and regulate data segment insertion to delay insertion of a data segment subsequent in order until a signal is received designating exit from the data switch of a data segment previous in order.
Abstract: A communication apparatus comprises a controlled switch capable of communicating scheduled messages and interfacing to a plurality of devices, and an uncontrolled switch capable of communicating unscheduled messages and interfacing to the plurality of devices. The uncontrolled switch generate signals that schedule the messages in the controlled switch.
Abstract: In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.
Abstract: A family of interconnect structures, switches that exploit the interconnect structures to attain scalability, low latency, and single-chip implementations. The disclosed interconnect structures and switches support a wide variety of applications including supercomputer interconnects, LAN switches, IP and ATM switches, telephony central office switching, video on demand servers, interconnects for mainframe database servers, high-speed workstation interconnects, and many others that are known to those having ordinary skill in the art.
Abstract: An interconnect structure substantially improves operation of an information concentrator through usage of single-bit routing through control cells using a control signal. The interconnect structure and operating technique support wormhole routing and flow of messages. Message packets are always buffered within the structure and never discarded, so that any packet that enters the structure is guaranteed to exit. In one example, the interconnect structure includes a ribbon of interconnect lines connecting a plurality of nodes in nonintersecting paths. The ribbon of interconnect lines winds through a plurality of levels from the source level to the destination level. The number of turns of a winding decreases from the source level to the destination level. The interconnect structure further includes a plurality of columns formed by interconnect lines coupling the nodes across the ribbon in cross-section through the windings of the levels.
Abstract: A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip.