Abstract: An interconnect structure substantially improves operation of an information concentrator through usage of single-bit routing through control cells using a control signal. The interconnect structure and operating technique support wormhole routing and flow of messages. Message packets are always buffered within the structure and never discarded, so that any packet that enters the structure is guaranteed to exit. In one example, the interconnect structure includes a ribbon of interconnect lines connecting a plurality of nodes in nonintersecting paths. The ribbon of interconnect lines winds through a plurality of levels from the source level to the destination level. The number of turns of a winding decreases from the source level to the destination level. The interconnect structure further includes a plurality of columns formed by interconnect lines coupling the nodes across the ribbon in cross-section through the windings of the levels.

Abstract: A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip.