Patents Assigned to Intercon Technologies, Inc.
  • Patent number: 7281535
    Abstract: Improved systems and methods for singulating a substrate into a plurality of integrated circuit devices are disclosed. One aspect of the invention corresponds to a fixture that holds the substrate during the dicing process. Another aspect of the invention pertains to a nozzle assembly that provides better fluid flow over the cutting blades. Another aspect of the invention corresponds to a nozzle adjustment assembly that helps position the nozzles relative to the blades. Another aspect of the invention corresponds to spacers that reduce the problem of imbalance caused by fluid retained therein. Yet another aspect pertains to the composition of the fluid, which is distributed by the nozzle assembly to the blades.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: October 16, 2007
    Assignees: Towa Intercon Technology, Inc., Koninklijke Philips Electronics, N.V.
    Inventors: Chris Mihai, Teang K Khor, Marcus F. Donker, Leonardus A. E. Gemert
  • Patent number: 7153186
    Abstract: Techniques for singulating a substrate into a plurality of component parts is disclosed. The singulation techniques include generating a jet stream in order to cut through large components so as to produce smaller components. The techniques are particularly suitable for singulating surface mount devices such as chip scale packages, ball grid arrays (BGA), flip chips, lead less packages (QFN) and the like. The techniques are also suitable for singulating photonic devices.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Towa Intercon Technology, Inc.
    Inventors: Ross Popescu, Clarence Tamargo, Shan Jiang
  • Publication number: 20060194514
    Abstract: Techniques for singulating a substrate into a plurality of component parts is disclosed. The singulation techniques include generating a jet stream in order to cut through large components so as to produce smaller components. The techniques are particularly suitable for singulating surface mount devices such as chip scale packages, ball grid arrays (BGA), flip chips, lead less packages (QFN) and the like. The techniques are also suitable for singulating photonic devices.
    Type: Application
    Filed: April 17, 2006
    Publication date: August 31, 2006
    Applicant: Towa Intercon Technology, Inc., A California Corporation
    Inventors: Ross Popescu, Clarence Tamargo, Shan Jiang
  • Patent number: 7059940
    Abstract: Techniques for singulating a substrate into a plurality of component parts is disclosed. The singulation techniques include generating a jet stream in order to cut through large components so as to produce smaller components. The techniques are particularly suitable for singulating surface mount devices such as chip scale packages, ball grid arrays (BGA), flip chips, lead less packages (QFN) and the like. The techniques are also suitable for singulating photonic devices.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: June 13, 2006
    Assignee: Towa Intercon Technology, Inc.
    Inventors: Seill Seo, Steven Tay, Shan Jiang
  • Publication number: 20050126472
    Abstract: Techniques for singulating a substrate into a plurality of component parts is disclosed. The singulation techniques include generating a jet stream in order to cut through large components so as to produce smaller components. The techniques are particularly suitable for singulating surface mount devices such as chip scale packages, ball grid arrays (BGA), flip chips, lead less packages (QFN) and the like. The techniques are also suitable for singulating photonic devices.
    Type: Application
    Filed: August 30, 2004
    Publication date: June 16, 2005
    Applicant: Towa Intercon Technology, Inc.
    Inventors: Ross Popescu, Clarence Tamargo, Shan Jiang
  • Patent number: 6688300
    Abstract: The invention relates, in one embodiment, to an arrangement configured to support a substrate during a dicing process. The substrate has thereon a first substrate side and a second substrate side. The first substrate side is smoother than the second substrate side. The arrangement includes a nest having a first nest side and a second nest side. The nest includes a grid which defines at least one nest opening. The nest opening has an opening area that is smaller than an area of a die diced from the substrate. The arrangement further includes a vacuum retainer plate having thereon at least one vacuum pedestal. The vacuum pedestal has an upper surface formed of a resilient material. The vacuum pedestal is configured to be disposed through the nest opening when the nest is mated with the vacuum retainer plate.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: February 10, 2004
    Assignee: Intercon Technologies, Inc.
    Inventor: Alois Tieber
  • Patent number: 6638791
    Abstract: A nest arrangement which is configured to support a substrate during a dicing process, and methods for using such a nest arrangement, are disclosed. According to one aspect of the present invention, a nest arrangement supports a substrate, which includes a first side and a second side, the first side being smoother than the second side. This nest arrangement includes a nest having a first side and a second side disposed above a vacuum retainer plate. The nest includes a locator pin for aligning the substrate with the nest when said substrate is disposed on the first side of the nest, and has a grid which defines at least one nest opening with an opening area that is smaller than an area of a chip diced from the substrate, and at least one retainer wall disposed on the first side proximate the opening area. The vacuum retainer plate has thereon at least one vacuum pedestal, which is configured to be disposed through the nest opening when the nest is mated with the vacuum retainer plate.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: October 28, 2003
    Assignee: Intercon Technology, Inc.
    Inventor: Alois Tieber