Abstract: The present invention is related to a method and apparatus for blindly equalizing received signals in the time domain based on independent component analysis (ICA). Received signals are demodulated and over-sampled by a rate at least twice the symbol rate to populate a mixing matrix. The received signal samples are cast into the form of a signal separation problem as represented by the multiplication of the mixing matrix with the transmitted symbols such that the unknowns can be solved by ICA. Applying ICA to the received signal samples provides a de-mixing matrix which can be multiplied by the received signal samples to estimate the transmitted symbol sequence. The proposed ICA-based equalization method simultaneously corrects other transmission imperfections, such as DC-offset, carrier phase offset and in-phase and quadrature imbalance, all in the time domain. As an alternative to over-sampling, multiple copies of the received signals are received via a plurality of antennas.

Abstract: A system and method for supporting mobile Internet communication is provided which employs a plurality of Routers and a plurality of Mobile Nodes (MNs). Each Router has a unique communication address. Each MN is associated with a home Router. Each Router has an associated Mobile Node Location List identifying each MN for which the Router is the home Router and the communication address of a Router corresponding to a current location of each such MN. Each MN is movable from an old location where the MN communicates with the Internet via one Router to a current location where the MN communicates with the Internet via a different Router. Communication at the current location via the different Router is established by communicating to the MN's home Router the communication address of the different Router as the communication address corresponding to the MN's current location.

Abstract: A transmission apparatus for generating a complex four-phase pseudo-random sequence having I and Q portions includes a shift register and an accumulator. The shift register has a plurality of positions. The accumulator has a first input for receiving an output from the shift register and a second input for receiving a predetermined value. The accumulator combines the data received via the first and second inputs and outputs the combined data to the shift register. Bits from a first predetermined position within the shift register are used to generate the I portion of the sequence and bits from a second predetermined position within the shift register are used to generate the Q portion of the sequence.