Abstract: In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate circuits are interrogated by a voting circuit which determines the existence of a faulted circuit in order to eliminate the faulted circuit from the operation of the FPGA. In this manner, without physical addition of redundant circuits, fault tolerancy for the FPGA is provided to minimize the cost, weight, volume, heat and energy associated issues of conventional redundance techniques.

Abstract: There is provided a reconfigurable computing system (10) for performing both script and rule processing. Reconfigurable computing system (10) generally includes a script processing module (100); a reconfigurable rule processing module (200); and a controller module (300). Reconfigurable rule processing module (200) includes a working memory portion (210a, 210b), a rule evaluation portion (230), and an interconnection portion (220, 222) for coupling together the working memory (210a, 210b) and rule evaluation (230) portions. The rule evaluation portion (230) is formed by a plurality of inference cells, each of which is configured to generate an inference signal responsive to at least a portion of an input signal. Controller module (300) which is coupled to both script processing module (100) and rule processing module (200) is capable of automatically actuating reconfiguration of rule processing module (200) in accordance with predetermined processing logic.