Abstract: An interface for biphase data communication systems utilizing serial transmissions between a central control unit and a peripheral device. A ROM-latch network serving as a sequencer is utilized as a bi-directional biphase serial/TTL parallel translator. In the receiver mode the ROM-latch will step through a specific operational sequence for detecting an appropriate header and controlling a TTL parallel translation of the serial biphase data. In the transmitter mode the ROM-latch is used to reconstruct the header sequence prior to retranslating and transmitting the TTL parallel data in serial biphase format. A receiver clock generator circuit is provided for generating clock pulses for the ROM-latch in synchronism with the incoming biphase transmissions. A transmitter level converter defines the waveforms for the biphase data transmitted from the interface and is designed to provide a predistortion pulse at each voltage level transition.

Abstract: An interface system for expanding the number of device input ports and compatable with the message format and bus structure of a standard interface, namely the IEEE standard 488, has address decoding logic which identifies the expansion system and is operative to select, in accordance with an incoming message on the bus, which of several ports is to transmit or receive messages via the bus. Under control of the port identification message and strobe signals obtained from the handshake control logic of the expansion system, a sequence containing a predetermined number of bytes of port data is transmitted to the bus. The port data bytes may be coded in various formats, desirably BCD, which is compatable with the digital output format of many devices which may be interconnected and interfaced by the expansion system with the bus.

Abstract: Weighted modulus numbering apparatus is capable of printing composite numbers consisting of serial identification numbers and accompanying check digits which are determined in accordance with a system where the check digits for certain identification numbers may be invalid, as by requiring a two-digit number rather than an allowable single-digit number. The check digits are generated in the form of digital (for example, binary) words and decoded to provide a signal representing the validity or invalidity of the check digit. A memory stores the check digit words and a bit representing the validity/invalidity of the check digit. The decoding of an invalid check digit operates to cause the word representing the check digit for the next successive identification number to be stored with the valid/invalid bit in memory. The numbering machine, which presents the successive identification numbers for printing, is caused to increment twice in response to a signal representing an invalid check digit.