Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.
Type:
Grant
Filed:
August 20, 2010
Date of Patent:
October 30, 2012
Assignee:
Internantional Business Machines Corporation
Inventors:
Brent A. Anderson, Suk Hoon Ku, Edward J. Nowak