Patents Assigned to Internatiional Business Machines Corporation
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Patent number: 11411739Abstract: A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.Type: GrantFiled: February 7, 2019Date of Patent: August 9, 2022Assignee: Internatiional Business Machines CorporationInventors: Frank R. Libsch, Seiji Munetoh, Abhilash Narendra, Ghavam G. Shahidi
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Patent number: 9607716Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.Type: GrantFiled: April 9, 2014Date of Patent: March 28, 2017Assignee: Internatiional Business Machines CorporationInventors: Charles A. Kilmer, Warren E. Maule, Saravanan Sethuraman
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Publication number: 20150054592Abstract: A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicants: University of South Carolina, INTERNATIIONAL BUSINESS MACHINES CORPORATIONInventors: Barbara S. DEWITT, Essam MINA, BM Farid RAHMAN, Guoan WANG
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Publication number: 20140320555Abstract: A pixel circuit for an active matrix organic light-emitting diode display system includes a first input node, a second input node, first power supply node, a second power supply node, a triode switch circuit, a storage capacitor, an organic light emitting diode, and a resistive element. The triode switch circuit is connected to the first and second input nodes. The storage capacitor is connected between an output of the triode switch circuit and the second power supply node. The organic light-emitting diode is connected between the output of the triode switch circuit and the second power supply node. The first resistive element is connected between the output of the triode switch circuit and the first power supply node.Type: ApplicationFiled: August 19, 2013Publication date: October 30, 2014Applicant: Internatiional Business Machines CorporationInventors: Bahman Hekmatshoartabari, Davood Shahrjerdi
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Publication number: 20120217479Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: Internatiional Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
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Publication number: 20100031168Abstract: A mechanism for displaying web pages to a user, receives an HTML code of the web page to be displayed, and interprets the HTML code. The mechanism interprets a computer program code embedded in the HTML code of the web page to be displayed. The embedded code includes an indication of at least one menu option to be displayed upon request of the user. Responsive to a command from the user, a pop-up menu containing the at least one menu option is displayed to the user.Type: ApplicationFiled: March 22, 2007Publication date: February 4, 2010Applicant: Internatiional Business Machines CorporationInventors: Mario Loriedo, Tommaso Mazzarotto, Sandro Piccini
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Publication number: 20080300865Abstract: In a natural language, mixed-initiative system, a method of processing user dialogue can include receiving a user input and determining whether the user input specifies an action to be performed or a token of an action. The user input can be selectively routed to an action interpreter or a token interpreter according to the determining step.Type: ApplicationFiled: April 30, 2008Publication date: December 4, 2008Applicant: INTERNATIIONAL BUSINESS MACHINES CORPORATIONInventors: Rajesh Balchandran, Linda Boyer
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Patent number: 6980018Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.Type: GrantFiled: April 29, 2004Date of Patent: December 27, 2005Assignee: Internatiional Business Machines CorporationInventors: Hung C. Ngo, Jente B. Kuang, Kevin J. Nowka
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Patent number: 5758120Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible field in each page table entry and this reference bit is utilized to indicate if an associated system memory location has been accessed for a read or write operation.Type: GrantFiled: August 20, 1996Date of Patent: May 26, 1998Assignee: Internatiional Business Machines CorporationInventors: James Allan Kahle, John Stephen Muhich, Richard Raphael Oehler, Edward John Silha