Abstract: Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a system of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.

Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Abstract: A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.

Abstract: An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Abstract: A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

Abstract: A method and system for photomask pattern generation is provided, and more specifically, a method and system for feature function aware priority printing is provided. The method of printing a photolithographic mask includes fracturing mask design data into write shapes that are multiples of a spot size and passing fractured mask design data to a write tool. Additionally, the method includes writing one or more non-critical shapes according to one or more time-saving rules.

Abstract: Provided are a method, system, and program for searching documents for ranges of numeric values. Document identifiers for documents are accessed, wherein the documents include at least one value that is a member of a set of values. A number of posting lists are generated. Each posting list is associated with a range of consecutive values within the set of values and includes document identifiers for documents having values within the range of consecutive values associated with the posting list. Each document identifier is associated with one value in the set of values included in the document identified by the document identifier. The generated posting lists are stored.

Abstract: A system and method for authenticating a host on a network enables the host to update IP configuration and internal configuration of a storage controller connected to the network. The host has an algorithm to decrypt a security key supplied by the storage controller. The host broadcasts a discovery command which includes an IP address of the host and a service requested by the host. The discovery command conforms to a proprietary discovery command protocol. In response to the discovery command, the host receives a response from a storage controller which is able to provide the requested service. The response includes a WWN, IP configuration and a security key of the storage controller, and conforms to the discovery command protocol. Next, the host decrypts the security key received from the storage controller using the decryption algorithm, and sends an updated IP configuration to the storage controller along with the security key for authentication.

Abstract: A method for managing operator services comprises the steps of: compressing respective voice calls between a public switched telephone network (PSTN) and a local area network (LAN) of telephone operator work stations into respective streams of digital voice data packets; multiplexing the respective streams of digital voice data packets; transmitting the multiplexed streams of the respective voice data packets between the PSTN and the LAN over a single digital data transmission line; demultiplexing the respective streams of the digital voice data packets transmitted over the single digital data transmission line; and, decompressing the demultiplexed streams of the digital voice data packets.

Abstract: A method of planarizing a dielectric coating applied over an underlying structure on an integrated circuit wafer employs a two-step chemical mechanical polishing (CMP) process. The underlying structure is characterized as having elevated areas and recessed areas. The wafer can be prepared by applying a first polish stop on the elevated areas, then depositing a layer of dielectric over at least the recessed areas, and finally depositing a second polish stop over the resulting dielectric coating. In some applications a first polish stop is not required. The first step in the two-step CMP is polishing the second polish stop using a slurry that polishes the second polish stop until the second polish stop is substantially removed over the elevated areas. The second step is polishing the dielectric coating that remains using a second slurry that polishes the dielectric at a faster rate than it polishes either the second or first polish stop.

Abstract: A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.