Patents Assigned to International Busiess Machines Corporation
  • Patent number: 10552118
    Abstract: A computer-implemented method includes identifying a first set of utterances from a plurality of utterances. The plurality of utterances is associated with a conversation and transmitted via a plurality of audio signals. The computer-implemented method further includes mining the first set of utterances for a first context. The computer-implemented method further includes determining that the first context associated with the first set of utterances is not relevant to a second context associated with the conversation. The computer-implemented method further includes dynamically muting, for at least a first period of time, a first audio signal in the plurality of audio signals corresponding to the first set of utterances. A corresponding computer system and computer program product are also disclosed.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 4, 2020
    Assignee: International Busiess Machines Corporation
    Inventors: Tamer E. Abuelsaad, Gregory J. Boss, John E. Moore, Jr., Randy A. Rendahl
  • Patent number: 10216653
    Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 26, 2019
    Assignee: International Busiess Machines Corporation
    Inventors: Lakshminarayana Baba Arimilli, Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John David Irish, David J. Krolak, Lonny Lambrecht, Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, Curtis C. Wollbrink
  • Patent number: 8587905
    Abstract: In one general embodiment, a magnetic head comprises an inner module comprising an array of data readers; and first and second outer modules flanking the inner module. The outer modules are identical, each outer module comprising an array of data writers. A number of active data writers in each outer module is less than a number of active data readers in the inner module. For the first outer module, one of the active data writers is aligned with one of the data reader positioned towards a first end of the inner module array in a direction generally parallel to the path of tape travel thereacross. For the second outer module, one of the active data writers is aligned with one of the data readers positioned towards a second end of the inner module array in the direction generally parallel to the path of tape travel thereacross.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 19, 2013
    Assignee: International Busiess Machines Corporation
    Inventor: Peter VanderSalm Koeppe
  • Publication number: 20080283285
    Abstract: A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 20, 2008
    Applicant: INTERNATIONAL BUSIESS MACHINES CORPORATION
    Inventors: Roland Frech, Thomas-Michael Winkel, Erich Klink
  • Publication number: 20030093721
    Abstract: A disk array storage system and error recovery method wherein recovery from disk errors is achieved using automated selective power cycling. Initially, identification is made of a faulty disk drive in the array that exhibits an error condition in which the drive fails to perform a requested operation. The faulty disk drive is selectively power cycled while power to other disk drives in the array is maintained. Following the power cycling sequence, the requested operation is retried.
    Type: Application
    Filed: September 24, 2001
    Publication date: May 15, 2003
    Applicant: International Busiess Machines Corporation
    Inventors: Allen King, Davis Qi-Yu Chu