Abstract: B-Tree data is serialized to existing data for all types of workloads by converting a B-Tree data structure into a format capable of being stored and resurrected while containing all data stored in the B-Tree data structure and information relating to the B-Tree data structure. The serialized B-Tree data is divided into a plurality of sections. The serialized B-Tree data is stored into a plurality of buffers, where storing the B-Tree information section in a first binary buffer, the B-Tree key section in a second binary buffer, and the B-Tree data section in a third binary buffer. In the B-Tree data section, B-Tree data elements stored in the B-Tree data structure are saved, where a size of the B-Tree data section is equal to a total number of the B-Tree data elements in the B-Tree data structure multiplied by a size of each of the B-Tree data elements.

Abstract: A technique relates to a microwave device. A microwave system is configured to output a microwave readout signal, where the microwave system has an input and an output. An output microwave transmission line is connected to the output of the microwave system. A distributed Bragg reflector, integrated into a transmission line geometry, is configured as a low-loss infrared filter that blocks infrared radiation while allowing transmission of the microwave readout signal. The low-loss infrared filter is connected to the output microwave transmission line.

Abstract: An approach is provided for evaluating a potential post based on historical data. In the approach, historically highly rated attributes that to previously received highly rated posts are identified. The process receives a potential post from an online Subject Matter Expert (SME). The process analyzes the potential post, using a Natural Language Processing (NLP) routine performed by computer processors. The analysis identifies a lack of one or more of the historically highly rated attributes in the potential post. The process then notifies the SME, based on the analysis, regarding the lack of one or more of the historically highly rated attributes in the potential post.

Abstract: The invention comprises a computer-implemented process for managing computing resources provided to customers in an on-demand data center. The process comprises: providing a shared computing environment; providing to each customer one or more logical partitions of computing resources within the shared computing environment; allocating at least one processing engine to each logical partition; modeling a selected customer's resource utilization as a beta distribution; iteratively selecting a random resource utilization value from the beta distribution and, for each logical partition, calculating a processing engine differential; for each iteration, calculating a collective processing engine differential until the collective processing engine differential converges on an optimal processing engine differential; and adjusting the number of processing engines by the optimal processing engine differential to achieve an optimal free pool size.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Each node implements a respective routing strategy for routing data through the network, the routing strategies not necessarily being the same in every node. The routing strategies implemented in the nodes are dynamically adjusted during application execution to shift network workload as required. Preferably, adjustment of routing policies in selective nodes is performed at synchronization points. The network may be dynamically monitored, and routing strategies adjusted according to detected network conditions.

Abstract: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material.

Abstract: A method (and structure) for controlling a beam used to generate a pattern on a target surface includes generating a beam of charged particles and directing the beam to a mask surface and causing the beam to be either absorbed by or reflected from the mask surface, thereby either precluding or allowing the beam to strike the target surface, based on a reflection characteristic of the mask surface.

Abstract: Disclosed is a method for forming an optical mask that has reduced processing steps. The invention performs a first patterning of an opaque chrome layer to expose a first region of a transparent quartz substrate and ten etches the first region of the transparent quartz substrate through the chrome layer to create a phase shift region within the transparent quartz substrate. Next, the invention performs additional patterning of the opaque chrome layer to expose a second region of the transparent quartz substrate that is adjacent to the first region. This additional patterning process enlarges the opening formed in the opaque mask formed in the first patterning process. The first region and the second region comprise a continuous area of the transparent quartz substrate.

Abstract: A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.

Abstract: An electrical structure including a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.

Abstract: Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer.

Abstract: A method and apparatus for creating a schema definition from a language-specific metamodel of a data structure written in a legacy computer language involves walking through the nodes of the metamodel, and creating corresponding schema element objects in a schema tree that is serialized to create the schema definition. The creation of the schema element objects follows rules, and permits the definition of nested data structures having conjunctive-type and disjunctive-type membership.

Abstract: Methods, systems and computer program products are provided for transferring log data to a server over a wireless network from a plurality of remote devices. The server is configured to receive data from the plurality of remote devices. A transfer period is scheduled for transferring log data from a remote device to the server taking into account a wireless network signal strength of the remote device for the scheduled transfer period. The scheduled transfer period does not overlap a time when an estimated wireless network strength is too low to transfer the log data.

Abstract: A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

Abstract: A method of distributing and executing upgrade/installation instructions as data objects. These instructions can then be completed automatically requesting user interaction only when required. This method would allow someone with little knowledge of the application and/or internal implementation of said application to perform an upgrade to the application.

Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.

Abstract: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

Abstract: An in-situ wear indicator for detecting wear to at least one selected part in a semiconductor manufacturing environment. The indicator is manufactured in a selected material with a selected thickness so that the indicator degrades upon exposure to the semiconductor manufacturing process at a fixed rate relative to the wear of the selected part. The indicator displays a visual indication of wear which is discernible by an automated detection device.

Abstract: Method for providing slave direct memory access (DMA) support on a computer system bus that does not support slave devices, such as the personal computer interconnect or "PCI" bus. Using the method, an adapter card or microprocessor with a local DMA controller can be operated as a busmaster and simulate a system DMA controller which would normally be used during slave DMA operations. Alternatively, the method allows a local DMA controller to work with an existing system DMA controller so that application software receives the correct status when polling registers in the system DMA controller. The method allows the system DMA controller to operate as if the system DMA controller is controlling DMA transfers. In this way device contention between the system DMA controller and the local DMA controller is avoided.