Abstract: A Data Loss Prevention (DLP) system includes an automated method for tracking changes to a security classification (e.g., content category) associated with an artifact to determine whether an attempt is being made to subvert a DLP policy. The method exploits the basic principle that, depending on context, the classification of a particular artifact, or a change to an existing classification, may indicate an attempt to subvert the policy. According to the method, an artifact classification state machine is implemented within a DLP system. For each policy-defined content category on each artifact, the machine identifies a content category change that may be of interest, as defined by policy. When a change in a classification has occurred, an artifact notification event (or, more generally, a notification of the change in classification) is issued.

Abstract: A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.

Abstract: A method and system are provided for encapsulation and re-use of a model. A modeling platform creates a governance contract governing the exportation and modification of elements of the model by other models. In response to a request to import at least one element of the model into a second model, the modeling platform exports the requested at least one element by reference only if the element has a governance setting that allows for exportation. In response to a request to modify at least one imported element of the model in the second model, the modeling platform determines the governance setting for the element. Then, the modeling platform modifies the element by composing the modification in the second model only if the element has a governance setting that allows modification.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: A system and method for declaring variables during coding of a software program. The method includes, for each variable type, defining a unique string representing a variable declaration instruction and adapting a coding module wherein, when a string representing a variable declaration instruction is typed adjacent to a new variable name, the coding module automatically generates code for the corresponding variable declaration statement for a new variable having the new variable name and the specified variable type. The method further includes defining a reserved variable declaration area in the software program and placing any code generated by the coding module for the variable declaration statement into the reserved variable declaration area. Each unique string representing a variable declaration instruction may be a prefix or suffix that may be typed adjacent to the new variable name.

Abstract: A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

Abstract: A method for platform agnostic screen capture is provided. The method includes acquiring screen data from a computer having a display screen, where the screen data represents an image currently displayed on the display screen. The screen data is converted into a representation capable of being expressed in a plurality of software platforms. The representation of screen data is rendered into a vector graphics file that may be published to a plurality of platforms.

Abstract: In one general embodiment, an apparatus includes at least one first module configured for writing and/or reading data to and from a magnetic medium in a first format and/or first generation and writing data to the magnetic medium in a second format and/or second generation that is different than the first format and first generation. The apparatus also includes a supplemental module coupled to the first module, the supplemental module being configured for reading a magnetic medium having data written in the second format and/or the second generation.

Abstract: A configuration model for an existing software solution, which is distributed over a plurality of existing machines, is discovered. The model includes a plurality of configuration items, which in turn include a plurality of independent attributes and a plurality of dependent attributes, with the plurality of dependent attributes being derivable from the plurality of independent attributes based on a plurality of constraints. The configuration model is stored in a repository, together with disk images, resource configuration details, and logical names of pertinent ones of the existing machines. Specifications of new values of the independent attributes are obtained, and new values of the dependent attributes are computed from the new values of the independent attributes, based on executing the constraints on the configuration model.

Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.

Abstract: A memory heap is allocated to a contiguous range of memory. One end of the heap is designated as a small object area. The other end of the heap is designated as a large object area. When the two object areas grow, the small object area grows inward within the heap toward the large object area, and the large object area grows inward within the heap toward the small object area.

Abstract: A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

Abstract: Methods, systems, and products for delayed deletion of extended attributes associated with a file in a file system are provided. Embodiments include identifying a file to delete, moving an extended attribute directory associated with the file to a background deletion directory, deleting the file, and deleting in the background the extended attribute directory. Some embodiments also include deleting an ACL associated with the file.

Abstract: A first message published by a first publisher, including a message header and payload data, is received. The payload data within the first received message is identified, extracted, and stored. A second message published by a second publisher, including function data that provides a function to modify the payload data, is received. The function data within the second received message is identified, extracted, and stored. The extracted and stored payload data is modified using the stored function. A third message, including the modified payload data, is created for distribution to a subscriber configured to process the modified payload in the third message.

Abstract: Leveraging existing Binary Decision Diagrams (BDDs) to enhance circuit reductions in a system model representing a state machine as a netlist. The netlist is evaluated to determine the regions with the greatest potential reductions. BDD sweeping is performed to identify redundancies in the netlist. BDD rewriting implements the circuit reductions by replacing gates of the original netlist with more efficient equivalent logic.

Abstract: A method and circuit for implementing security protection with carbon nanotube based sensors for cryptographic applications, and a design structure on which the subject circuit resides are provided. A carbon nanotube layer is incorporated with a polymeric encapsulation layer of a security card. Electrical connections to the carbon nanotube layer are provided for electrical monitoring of electrical resistance of the carbon nanotube layer.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: A method and computer program product for pre-rendering web content is described. A method may comprise receiving, via a computing device, an implicit indication of a request for web content associated with a web element. The method may further comprise pre-rendering the web content associated with the web element based upon, at least in part, the implicit indication of the request for the web content.

Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.

Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.