Patents Assigned to International Business Machine Corporation
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Patent number: 7574642Abstract: A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.Type: GrantFiled: April 7, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Steven Ross Ferguson, Garrett Stephen Koch, Osamu Takahashi, Michael Brian White
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Patent number: 7574556Abstract: A storage system has a storage controller for an array of storage disks, the array being ordered in an sequence of write groups. A write cache is shared by the disks. The storage controller temporarily stores write groups in the write cache, responsive to write groups being written, and lists the write groups in order of their sequence in the array and in circular fashion, so that a lowest is listed next to a highest one of the write groups. The storage controller selects the listed write groups in rotating sequence. Such a write group is destaged from the write cache to the disk responsive to i) the selecting of the write group and ii) a state of a recency indicator for the write group, wherein the recency indicator shows recency of writing to the write group.Type: GrantFiled: March 20, 2006Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Binny Sher Gill, Dharmendra Shantilal Modha
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Patent number: 7572689Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.Type: GrantFiled: November 9, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Brian J. Greene, Rajesh Rengarajan
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Patent number: 7573284Abstract: Disclosed is a method and system for wafer/probe testing of integrated circuit devices after manufacture. The invention begins by testing an initial group of devices (e.g., integrated circuit chips) to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified by type of failure. Then, the invention retests the devices in the initial failing group to identify a retested passing group of devices that passed the retesting. Next, the invention analyzes the devices in the retested passing group which allows the invention to produce statistics regarding the likelihood that a failing device that failed the initial testing will pass the retesting according to the type of failure. Then, the invention evaluates these statistics to determine which types of failures have retest passing rates above a predetermined threshold.Type: GrantFiled: July 9, 2008Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventor: Akiko F. Balchiunas
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Patent number: 7574704Abstract: A system and method for reorganizing source code using frequency based instruction loop replication are provided. Code is reorganized based on the frequency of execution of blocks of the code so as to favor frequently executed blocks of code over rarely executed code with regard to subsequent optimizations. Frequently executed blocks of instructions are maintained within loop/switch statements and rarely executed blocks of instructions are removed from the loop/switch statements. The rarely executed blocks of instructions may be replicated after the loop/switch statement with a reference back to the loop/switch statement. In this way, when subsequent loop/switch statement optimizations are applied, the frequently executed blocks of instructions within the loop are more likely to benefit from such optimizations since the negative influence of the rarely executed blocks of instructions has been removed.Type: GrantFiled: October 21, 2004Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Mike Stephen Fulton, Christopher B. Larsson, Vijay Sundaresan
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Patent number: 7573709Abstract: A grounding spring for electromagnetic interference (EMI) suppression is interposed between a heat sink and a printed circuit board (PCB). The grounding spring comprises a conductive material having an opening formed at its base through which the heat sink makes thermal contact with an electronic module mounted on the PCB. The base makes electrical contact with a peripheral surface of the heat sink, and multiple-jointed spring fingers extend from the base to make electrical contact with conductive pads on the PCB. During compression, the movement of each spring finger's tip is substantially limited to the z-axis. Accordingly, the final installed location of the tip can be precisely controlled even when the grounding spring must accommodate a wide variety of installed heights of the heat sink relative to the PCB. Preferably, the spring fingers terminate with a concave tip that is less susceptible to sliding off the conductive pads.Type: GrantFiled: July 31, 2008Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Don Alan Gilliland, Max John Christopher Koschmeder
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Patent number: 7574529Abstract: A method for transferring data over a network operating in accordance with a protocol, such as the ESCON protocol, that supports a limited logical address range includes establishing a logical path over the network from a host or other device to a second device, such as a storage system, using path logical addresses within the given logical address range. A virtual path is created over the logical path to carry the data from the source to the target, wherein the target logical subsystem has a subsystem logical address which is outside the given logical address range.Type: GrantFiled: June 22, 2004Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Juan A Coronado, Bret W Holley, Lawrence C Blount
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Patent number: 7573300Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.Type: GrantFiled: January 15, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, George M. Braceras, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer
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Patent number: 7574526Abstract: A method for managing multicast groups with send-without-receive (SWR) joiners without the use of traps on creation and deletion of groups is provided. Group information is maintained continuously while the SWR member exists. When an SWR join is attempted and the group does not already exist, the group information (MLID) is marked as used and the first switch to which the SWR packets are sent is routed to discard all packets sent to the group. When receiving members join the group, the routing is updated so that the SWR member begins sending to the receiving members. When the last receiving member leaves the group, the first switch is again routed to discard the packets.Type: GrantFiled: July 31, 2003Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Vivek Kashyap, Gregory Francis Pfister
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Patent number: 7573665Abstract: Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.Type: GrantFiled: June 20, 2008Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Evangelos S. Eleftheriou, Robert Allen Hutchins, Glen Alan Jaquette, Sedat Oelcer
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Patent number: 7574667Abstract: A system, apparatus and method of appending a group of files to files on a clipboard of a desktop are provided. The system, apparatus and method include displaying a first window having an option that allows a group of files to be appended to files on the clipboard and asserting the option to append the files. The first window is ordinarily displayed after at least one file has been copied onto the clipboard and a second file is selected to be copied. In the case where at least one file has not already been copied onto the clipboard, a second window is displayed. The second window has an option that allows only one file or group of files to be copied onto the clipboard. The first window further contains an option that allows a file or a group of files to replace file or files already copied on the clipboard.Type: GrantFiled: September 19, 2008Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Neal Richard Marion, George F. Ramsay, III
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Patent number: 7572739Abstract: A semiconductor structure fabrication method for removing a tape physically attached to a device side of the semiconductor substrate by an adhesive layer of the tape, wherein the adhesive layer comprises an adhesive material. The method includes the step of submerging the tape in a liquid chemical comprising monoethanolamine or an alkanolamine for a pre-specified period of time sufficient to allow for a separation of the tape from the semiconductor substrate without damaging devices on the semiconductor substrate.Type: GrantFiled: January 26, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Steven R. Codding, Timothy C Krywanczyk, Steven G. Perrotte, Jason P. Ritter
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Patent number: 7574460Abstract: A minimized journaling mechanism stores minimized journal data in a format that allows for display and outputting the journal data in human-readable form. When a change to a record occurs, instead of writing only the changed bytes, all of the bytes in each field that changed are written to the journal, along with all of the bytes in each field selected to be always journaled. A default object is created with default data in all of the fields. When the journal entry needs to be output in human-readable form, the default object is read, and the minimized journal entry is then overlaid on the default object. The result is an object that contains default data in all non-selected fields that were not changed, with the journal data in all fields and that did change and in all fields that were selected to always be journaled.Type: GrantFiled: December 1, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Adam Thomas Stallman, Larry William Youngren
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Patent number: 7574671Abstract: A method and apparatus for selecting a desktop from a plurality of desktops for use upon turning on a computer system are provided. When the computer system is turned on, it is first determined whether there is more than one desktop available in the computer system. If so, the computer system determines whether a network address is associated with some or all of the available desktops by comparing its network address with the network addresses that are associated with the available desktops. If the computer system finds a network address that is the same as its own network address, the computer system then uses the desktop associated with the stored network address.Type: GrantFiled: July 18, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Susann Marie Keohane, Herman Rodriguez
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Patent number: 7574740Abstract: An intrusion detection system for detecting intrusion events in a computer network and assessing the vulnerability of the network components to the detected events. The intrusion detection system comprises a scanner, one or more sensors and a security console for operation within a networked computing environment. A sensor of the inventive intrusion detection system can monitor the networked computing environment for possible intrusion events representing an unauthorized access or use of the network resources. In response to detecting an intrusion event, the sensor can generate a scan request for handling by a scanner. This request initiates a scan of the target computer by the scanner to determine the vulnerability of the target to the attack. Based on this vulnerability analysis, the inventive intrusion detection system can evaluate the severity of the detected intrusion event and issue an alert having a priority corresponding to the severity of the intrusion.Type: GrantFiled: April 28, 2000Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventor: Peter H. Kennis
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Patent number: 7574708Abstract: Disclosed is an apparatus, method, and program product that enables distribution of operating system resources on a nodal basis in the same proportions as the expected system workload. The preferred embodiment of the present invention accomplishes this by assigning various types of weights to each node to represent their proportion of the overall balance within the system. Target Weights represent the desired distribution of the workload based on the existing proportions of processor and memory resources on each node. The actual workload balance on the system is represented by Current Weights, which the operating system strives to keep as close to the Target Weights as possible, on an ongoing basis. When the system is started, operating system services distribute their resources nodally in the same proportions as the Target Weights, and can request to be notified if the Target Weights ever change.Type: GrantFiled: March 4, 2004Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Lynn Keat Chung, Christopher Francois, Richard Karl Kirkman, Patrick Joseph McCarthy, Don Darrell Reed, Kenneth Charles Vossen
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Patent number: 7573810Abstract: Deadlocks are avoided in performing failovers in communications environments that include partnered interfaces. An ordered set of steps are performed to failover from one interface of a partnered interface to another interface of the partnered interface such that deadlocks are avoided.Type: GrantFiled: December 14, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Jay R. Herring, Aruna V. Ramanan, Karen F. Rash, legal representative, Nicholas P. Rash
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Patent number: 7572682Abstract: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.Type: GrantFiled: May 31, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein, Jack A. Mandelman, Louis L. Hsu
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Patent number: 7574563Abstract: Methods for serving data include maintaining an incomplete version of an object at a server and at least one fragment at the server. In response to a request for the object from a client, the incomplete version of the object, an identifier for a fragment comprising a portion of the object, and a position for the fragment within the object are sent to the client. After receiving the incomplete version of the object, the identifier, and the position, the client requests the fragment from the server using the identifier. The object is constructed by including the fragment in the incomplete version of the object in a location specified by the position.Type: GrantFiled: August 10, 2006Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: James Robert Harold Challenger, Louis Ralph Degenaro, Robert Filepp, Arun Kwangil Iyengar, Richard Pervin King
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Patent number: 7574439Abstract: A method and system for managing availability of a dependent thread to service a nested request is provided. A plurality of reply threads are maintained in a single thread pool. In addition, a counter is provided to track availability of a reply thread from the thread pool. A service thread that requires at least one reply thread to complete execution of a request must check the counter to determine availability of the reply thread prior to execution of the request. The process of determining availability of a reply thread prior to execution of a service thread request avoids initiating execution of a request that cannot be completed in a timely manner, or at all.Type: GrantFiled: May 20, 2004Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Craig F. Everhart, Venkateswararao Jujjuri, Ninad S. Palsule, James J. Seeger, Jr.